I noticed secondary CPUs sometimes fail to wake up, and the root cause seems that the "sev" instruction is sent before the preceding register write access is observed by the secondary CPUs.
The read-back of the accessed register cannot guarantee the order. This commit uses "dsb sy" barrier to ensure the order between the write access to UNIPHIER_SMPCTRL_ROM_RSV0 and the "sev" instruction.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c index 64412e0..3b75eaa 100644 --- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c +++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c @@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void) rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); - readq(rom_boot_rsv0); /* relax */
unmap_sysmem(rom_boot_rsv0);
uniphier_smp_setup();
- asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ + asm("dsb sy\n" /* Ensure the visibility of ROM_RSV0 write */ + "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ }