Re: [U-Boot] [PATCH v4 1/2] arm: dts: Add devicetree support for iMXQXP AI_ML board

On Fri, 19 Jul 2019 12:27:42 +0530 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org wrote:

Add devicetree support for iMXQXP AI_ML board from Einfochips.

Signed-off-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi | 117 +++++++++++++ arch/arm/dts/fsl-imx8qxp-ai_ml.dts | 181 +++++++++++++++++++++ 3 files changed, 299 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-ai_ml.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e6680e5e98..7834a158da 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -614,6 +614,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \

• fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-mek.dtb

Reviewed-by: Lukasz Majewski lukma@denx.de

Just out of curiosity - why ARM8 devices from iMX have dtb naming convention starting from 'fsl-' ?

With other boards we strive to have 'imx6q-'*.dts, 'imx53-'*.dts, etc?

diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi new file mode 100644 index 0000000000..3ca53bb945 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright 2019 Linaro Ltd.
• */

+&{/imx8qx-pm} {

• u-boot,dm-spl;

+};

+&mu {

• u-boot,dm-spl;

+};

+&clk {

• u-boot,dm-spl;

+};

+&iomuxc {

• u-boot,dm-spl;

+};

+&pd_lsio {

• u-boot,dm-spl;

+};

+&pd_lsio_gpio0 {

• u-boot,dm-spl;

+};

+&pd_lsio_gpio1 {

• u-boot,dm-spl;

+};

+&pd_lsio_gpio2 {

• u-boot,dm-spl;

+};

+&pd_lsio_gpio3 {

• u-boot,dm-spl;

+};

+&pd_lsio_gpio4 {

• u-boot,dm-spl;

+};

+&pd_lsio_gpio5 {

• u-boot,dm-spl;

+};

+&pd_lsio_gpio6 {

• u-boot,dm-spl;

+};

+&pd_lsio_gpio7 {

• u-boot,dm-spl;

+};

+&pd_conn {

• u-boot,dm-spl;

+};

+&pd_conn_sdch0 {

• u-boot,dm-spl;

+};

+&pd_conn_sdch1 {

• u-boot,dm-spl;

+};

+&pd_conn_sdch2 {

• u-boot,dm-spl;

+};

+&gpio0 {

• u-boot,dm-spl;

+};

+&gpio1 {

• u-boot,dm-spl;

+};

+&gpio2 {

• u-boot,dm-spl;

+};

+&gpio3 {

• u-boot,dm-spl;

+};

+&gpio4 {

• u-boot,dm-spl;

+};

+&gpio5 {

• u-boot,dm-spl;

+};

+&gpio6 {

• u-boot,dm-spl;

+};

+&gpio7 {

• u-boot,dm-spl;

+};

+&lpuart2 {

• u-boot,dm-spl;

+};

+&usdhc1 {

• u-boot,dm-spl;

+};

+&usdhc2 {

• u-boot,dm-spl;

+}; diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml.dts b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts new file mode 100644 index 0000000000..aa85caaff5 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright 2018 Einfochips
• • Copyright 2019 Linaro Ltd.
• */

+/dts-v1/;

+#include "fsl-imx8qxp.dtsi" +#include "fsl-imx8qxp-ai_ml-u-boot.dtsi"

+/ {

• model = "Einfochips i.MX8QXP AI_ML";
• compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
• chosen {

• bootargs = "console=ttyLP2,115200
  

earlycon=lpuart32,0x5a080000,115200";

• stdout-path = &lpuart2;
  

• };
• memory@80000000 {

• device_type = "memory";
  

• reg = <0x00000000 0x80000000 0 0x80000000>;
  

• };

+};

+&lpuart0 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_lpuart0>;
• status = "okay";

+};

+&lpuart1 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_lpuart1>;
• status = "okay";

+};

+&lpuart2 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_lpuart2>;
• status = "okay";

+};

+&lpuart3 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_lpuart3>;
• status = "okay";

+};

+&fec1 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_fec1>;
• phy-mode = "rgmii";
• phy-handle = <&ethphy0>;
• fsl,ar8031-phy-fixup;
• fsl,magic-packet;
• phy-reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
• phy-reset-duration = <10>;
• phy-reset-post-delay = <150>;
• status = "okay";
• mdio {

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• ethphy0: ethernet-phy@0 {
  

• 	compatible = "ethernet-phy-ieee802.3-c22";
  

• 	reg = <0>;
  

• };
  

• };

+};

+/* LS-I2C1 */ +&i2c1 {

• #address-cells = <1>;
• #size-cells = <0>;
• clock-frequency = <100000>;
• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_lpi2c1>;
• status = "okay";

+};

+&usdhc1 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_usdhc1>;
• bus-width = <4>;
• no-sd;
• #address-cells = <1>;
• #size-cells = <0>;
• status = "okay";

+};

+&usdhc2 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_usdhc2>;
• bus-width = <4>;
• cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
• status = "okay";

+};

+&iomuxc {

• pinctrl_fec1: fec1grp {

• fsl,pins = <
  

SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0

SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0

SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020

SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020

SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020

SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020

SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020

SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020

SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020

SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020

SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020

SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020

SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020

SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020

SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020

SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020

• >;
  

• };
• pinctrl_lpi2c1: lpi2c1grp {

• fsl,pins = <
  

SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021

SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021

• >;
  

• };
• pinctrl_lpuart0: lpuart0grp {

• fsl,pins = <
  

SC_P_UART0_RX_ADMA_UART0_RX 0X06000020

SC_P_UART0_TX_ADMA_UART0_TX 0X06000020

• >;
  

• };
• pinctrl_lpuart1: lpuart1grp {

• fsl,pins = <
  

SC_P_UART1_RX_ADMA_UART1_RX 0X06000020

SC_P_UART1_TX_ADMA_UART1_TX 0X06000020

• >;
  

• };
• pinctrl_lpuart2: lpuart2grp {

• fsl,pins = <
  

SC_P_UART2_RX_ADMA_UART2_RX 0X06000020

SC_P_UART2_TX_ADMA_UART2_TX 0X06000020

• >;
  

• };
• pinctrl_lpuart3: lpuart3grp {

• fsl,pins = <
  

SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020

SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020

• >;
  

• };
• pinctrl_usdhc1: usdhc1grp {

• fsl,pins = <
  

SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041

SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021

SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021

SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021

SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021

SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021

• >;
  

• };
• pinctrl_usdhc2: usdhc2grp {

• fsl,pins = <
  

SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041

SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021

SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021

SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021

SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021

SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021

SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021

• >;
  

• };

+};

Best regards,

Lukasz Majewski

--

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