Hi Mit Matelske,
I believe I made the changes to our FPGA that the eval's CPLD did when the FCFG gets switched to 1 (bringing up flash enable at reset). Since we have a smaller flash, I am putting the u-boot.bin at 0xFFE00000 (0xFFF00000 for the original Freescale u-boot), the base address for our flash. But I'm still not having any luck.
Look at p33 for a logic analyzer power-on reset trace: http://www.ovro.caltech.edu/~dwh/carma_board/powerpc_mpc8349e.pdf
When your board boots, assuming you have the configuration reset words pin strapping set to read from the local bus, the processor will read the RCWs starting from 'address zero' on CS#0, i.e., from the beginning of your flash.
If you have BMS = 0, then the reset vector will be 100h.
If you have BMS = 1, then the reset vector will be FFF0_0100h.
The default memory window during boot is setup 8MB from the end of flash, i.e., starting at FF80_0000h.
Your flash is 4Mx16 = 8MB, so it decodes in the 8MB window (a smaller flash would alias within the window, and a larger flash would not be completely visible).
Your U-Boot image should be placed at FFF0_0000h, since the reset vector is located 100h into the image. If you look at the image, it probably has RCWs in it, however, they do nothing in that location, the RCWs must be located in the first sector on the Flash.
Cheers, Dave