Fix: db64360.c: In function 'debug_led': db64360.c:413:6: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_real_open': mv_eth.c:424:6: warning: variable 'port_status' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_stop': mv_eth.c:642:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_xmit': mv_eth.c:718:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_receive': mv_eth.c:803:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_get_stats': mv_eth.c:902:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_update_stat': mv_eth.c:930:24: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c:929:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_print_stat': mv_eth.c:1011:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'eth_clear_mib_counters': mv_eth.c:2068:15: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'check_dimm': sdram_init.c:289:50: warning: variable 'trrd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:37: warning: variable 'tras_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:24: warning: variable 'trcd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:8: warning: variable 'trp_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:279:34: warning: variable 'devicesForErrCheck' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'setup_sdram': sdram_init.c:1256:13: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'initdram': sdram_init.c:1735:25: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c:1733:14: warning: variable 's1' set but not used [-Wunused-but-set-variable] sdram_init.c:1733:6: warning: variable 's0' set but not used [-Wunused-but-set-variable]
Note: no attempt was make to clean up the mess coding style and other issues in sdram_init.c
Signed-off-by: Wolfgang Denk wd@denx.de --- WARNING: space prohibited between function name and open parenthesis '(' WARNING: line over 80 characters WARNING: unnecessary whitespace before a quoted newline ... total: 0 errors, 101 warnings, 1327 lines checked
NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX MULTISTATEMENT_MACRO_USE_DO_WHILE
Warnings ignored, no further cleanup attempted.
board/Marvell/db64360/db64360.c | 3 +- board/Marvell/db64360/mv_eth.c | 33 +-- board/Marvell/db64360/sdram_init.c | 517 +++++++++++++++++------------------- 3 files changed, 254 insertions(+), 299 deletions(-)
diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c index 35b695e..5183466 100644 --- a/board/Marvell/db64360/db64360.c +++ b/board/Marvell/db64360/db64360.c @@ -34,6 +34,7 @@ #include "../include/mv_gen_reg.h" #include <net.h> #include <netdev.h> +#include <linux/compiler.h>
#include "eth.h" #include "mpsc.h" @@ -410,7 +411,7 @@ int checkboard (void) void debug_led (int led, int mode) { volatile int *addr = 0; - int dummy; + __maybe_unused int dummy;
if (mode == 1) { switch (led) { diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index 30304b0..6340585 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -421,7 +421,7 @@ static int mv64360_eth_real_open (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; unsigned int port_num; - u32 port_status, phy_reg_data; + u32 phy_reg_data;
ethernet_private = (ETH_PORT_INFO *) dev->priv; /* ronen - when we update the MAC env params we only update dev->enetaddr @@ -519,7 +519,7 @@ static int mv64360_eth_real_open (struct eth_device *dev) */
MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); + MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
/* Check Link status on phy */ eth_port_read_smi_reg (port_num, 1, &phy_reg_data); @@ -637,15 +637,6 @@ static int mv64360_eth_free_rx_rings (struct eth_device *dev)
int mv64360_eth_stop (struct eth_device *dev) { - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - /* Disable all gigE address decoder */ MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); @@ -715,7 +706,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; ETH_FUNC_RET_STATUS status; struct net_device_stats *stats; @@ -724,7 +714,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num;
stats = port_private->stats;
@@ -800,15 +789,12 @@ int mv64360_eth_receive (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; struct net_device_stats *stats;
- ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats;
while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == @@ -899,12 +885,10 @@ static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num;
mv64360_eth_update_stat (dev);
@@ -926,13 +910,10 @@ static void mv64360_eth_update_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy;
ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats;
/* These are false updates */ @@ -955,12 +936,12 @@ static void mv64360_eth_update_stat (struct eth_device *dev) * But the unsigned long in PowerPC and MIPS are 32bit. So the next read * is just a dummy read for proper work of the GigE port */ - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); stats->tx_bytes += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_HIGH); stats->rx_errors += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, @@ -1008,12 +989,10 @@ static void mv64360_eth_print_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num;
ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats;
/* These are false updates */ @@ -2065,13 +2044,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num) static void eth_clear_mib_counters (ETH_PORT eth_port_num) { int i; - unsigned int dummy;
/* Perform dummy reads from MIB counters */ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) - dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); + MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
return; } diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index d52d3f0..e62ed0c 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -44,15 +44,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#undef DEBUG #define MAP_PCI
-#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit (void); /* setup delay line of Mv64360 */ int mvDmaIsChannelActive (int); int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); @@ -276,7 +269,7 @@ return 0; #else uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; + unsigned int i, j, density = 1;
#ifdef DEBUG unsigned int k; @@ -286,17 +279,17 @@ return 0; uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128];
memclk = gd->bus_clk; tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
- DP (puts ("before i2c read\n")); + debug("before i2c read\n");
ret = i2c_read (addr, 0, 1, data, 128);
- DP (puts ("after i2c read\n")); + debug("after i2c read\n");
/* zero all the values */ memset (dimmInfo, 0, sizeof (*dimmInfo)); @@ -307,7 +300,7 @@ return 0; }
if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -385,48 +378,46 @@ return 0; switch (i) { case 2: /* Memory type (DDR / SDRAM) */ dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf + debug ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf + debug ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); -#endif + dimmInfo->slot); break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf + debug ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf + debug ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf + debug ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf + debug ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -434,33 +425,33 @@ return 0; switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug + ("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug + ("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug + ("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug + ("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -479,9 +470,9 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf + debug ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -494,49 +485,49 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/
/*#ifdef CONFIG_ECC */ case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf + debug ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + dimmInfo->errorCheckType); break; /* #endif */ /*------------------------------------------------------------------------------------------------------------------------------*/
case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf + debug ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf + debug ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf + debug ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf + debug ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -552,26 +543,26 @@ return 0;
dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug + ("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf + debug ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -591,34 +582,34 @@ return 0; ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug + ("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf + debug ("%d, ", - k + 1)); + k + 1); }
} else { /* DDR-RAM */
if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, ");
} - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -630,8 +621,8 @@ return 0; /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -639,8 +630,8 @@ return 0; hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -648,36 +639,36 @@ return 0; hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug + ("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -707,8 +698,8 @@ return 0; dimmInfo-> maxClSupported_DDR >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + debug + ("*** Change actual Cas Latencies cause of minimumCycleTime n"); } /* ronen - checkif the Dimm frequency compared to the Sysclock. */ if ((dimmInfo-> @@ -744,32 +735,32 @@ return 0; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf + debug ("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -779,7 +770,7 @@ return 0; /*------------------------------------------------------------------------------------------------------------------------------*/
case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -794,60 +785,60 @@ return 0; (data[i] & BIT6) >> 6; #ifdef DEBUG if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug + (" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug + (" - Buffered Address/Control Input: No \n");
if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug + (" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug + (" - Registered Address/Control Input: No \n");
if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug + (" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug + (" - On-Card PLL (clock): No \n");
if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug + (" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug + (" - Bufferd DQMB Inputs: No \n");
if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug + (" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug + (" - Registered DQMB Inputs: No \n");
if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug + (" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug + (" - Differential Clock Input: No \n");
if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug + (" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug + (" - redundant Row Addressing: No \n");
#endif break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -861,46 +852,46 @@ return 0; (data[i] & BIT5) >> 5; #ifdef DEBUG if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug + (" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug + (" - Early Ras Precharge: No \n");
if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug + (" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug + (" - AutoPreCharge: No \n");
if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug + (" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug + (" - Precharge All: No \n");
if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug + (" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug + (" - Write 1/ReadBurst: No \n");
if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug + (" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug + (" - lower VCC tolerance: 10 Percent \n");
if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug + (" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug + (" - upper VCC tolerance: 10 Percent \n");
#endif break; @@ -919,7 +910,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -932,9 +923,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -951,7 +942,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -964,9 +955,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -983,12 +974,12 @@ return 0; trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf + tmemclk, tmemclk / 100, tmemclk % 100); + debug ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1002,12 +993,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1021,12 +1009,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1035,41 +1020,41 @@ return 0; tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + dimmInfo->minRasPulseWidth, tras_clocks);
break; /*------------------------------------------------------------------------------------------------------------------------------*/
case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf + debug ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug + ("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1095,9 +1080,9 @@ return 0; } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1122,9 +1107,9 @@ return 0; } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1149,9 +1134,9 @@ return 0; } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/
@@ -1176,9 +1161,9 @@ return 0; } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1194,8 +1179,6 @@ return 0; dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth) * dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; if ((dimmInfo->errorCheckType == 0x1) || (dimmInfo->errorCheckType == 0x2) || (dimmInfo->errorCheckType == 0x3)) { @@ -1217,7 +1200,7 @@ return 0; tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
/* try a CAS latency of 3 first... */
@@ -1236,11 +1219,11 @@ return 0; cal_val = 2; }
- DP (printf ("cal_val = %d\n", cal_val)); + debug("cal_val = %d\n", cal_val);
/* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1272,13 +1255,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
/* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n");
/* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); }
/* SDRAM configuration */ @@ -1329,12 +1312,12 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); break; } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + debug("calculated refresh interval %0x\n", sdram_config_reg);
/* make sure the refresh value is only 14 bits */ if (sdram_config_reg > 0x1fff) sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + debug("adjusted refresh interval %0x\n", sdram_config_reg);
/* we want physical bank interleaving and */ /* virtual bank interleaving enabled so do nothing */ @@ -1344,30 +1327,30 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs == 1) { /* it's registered DRAM, so set the reg. DRAM bit */ sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); + debug("Enabling registered DRAM bit\n"); } /* turn on DRAM ECC? */ #ifdef CONFIG_MV64360_ECC if (info->errorCheckType == 0x2) { /* DRAM has ECC, so turn it on */ sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* set the data DQS pin configuration */ switch (info->sdramWidth) { case 0x4: /* memory is x4 */ sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); + debug("Data DQS pins set for 16 pins\n"); break; case 0x8: /* memory is x8 or x16 */ case 0x10: sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); + debug("Data DQS pins set for 8 pins\n"); break; case 0x20: /* memory is x32 */ /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); + debug("Data DQS pins set for 2 pins\n"); break; default: /* memory width unsupported */ printf ("DRAM chip width is unknown!\n"); @@ -1390,23 +1373,23 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
/* write the value into the SDRAM configuration register */ GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf + debug ("OOOOOOOOO sdram_conf 0x1400: %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG));
/* SDRAM open pages control keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf + debug ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
/* SDRAM set CAS Latency according to SPD information */ switch (info->memoryType) { @@ -1419,7 +1402,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Calculate the settings for SDRAM mode and Dunit control low registers */ /* Values set according to technical bulletin TB-92 rev. c */ case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); switch (info->maxClSupported_DDR) { case DDR_CL_3: tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ @@ -1428,18 +1411,18 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x05110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */
if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ tmp_dunit_control_low = 0x2C1107F2; else tmp_dunit_control_low = 0x3C1107d2; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2_5: @@ -1449,9 +1432,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x25110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */
if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1460,9 +1443,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x1B1107d2; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2: @@ -1472,9 +1455,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x04110051; else tmp_dunit_control_low = 0x03110051; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */
if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1483,9 +1466,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x3B1107d2; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_1_5: @@ -1495,9 +1478,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x24110051; else tmp_dunit_control_low = 0x23110051; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */
if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1506,9 +1489,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x1A1107d2; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break;
@@ -1528,8 +1511,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); }
/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ @@ -1538,8 +1521,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); }
/*------------------------------------------------------------------------------ */ @@ -1549,29 +1532,29 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* program this with the default value */ tmp = 0x02; /* power-up default address select decoding value */
- DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); /* figure out the DRAM chip size */ sdram_chip_size = (1 << (info->numOfRowAddresses + info->numOfColAddresses)); sdram_chip_size *= info->sdramWidth; sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + debug("computed sdram chip size is %#lx\n", sdram_chip_size); /* divide sdram chip size by 64 Mbits */ sdram_chip_size = sdram_chip_size / 0x4000000; switch (sdram_chip_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: @@ -1582,15 +1565,15 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
/* SDRAM address control */ GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf + debug ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); + tmp);
/* ------------------------------------------------------------------------------ */ /* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf + debug ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x11511220)); + 0x11511220); GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
@@ -1602,42 +1585,38 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf + debug ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); }
/* Use buffer 1 to return read data to the CPU * Page 426 MV64360 */ tmp |= (1 << 26); - DP (printf + debug ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf + GTREGREAD (SDRAM_CONFIG)); + debug ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG));
/* SDRAM timing To_do: */ /* ------------------------------------------------------------------------------ */
- DP (printf + debug ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0x9)); + 0x9); GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9);
- DP (printf + debug ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
- DP (printf - indent: Standard input:1450: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". Assuming "= *" - + debug ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
/* ------------------------------------------------------------------------------ */ @@ -1647,8 +1626,8 @@ indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". As /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug + ("\n*** Running a MRS cycle for bank %d ***\n", i);
/* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1656,17 +1635,17 @@ indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". As /* set SDRAM mode */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check);
/* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check);
/* unmap the bank */ memory_map_bank (i, 0, 0); @@ -1712,9 +1691,9 @@ long int dram_size (long int *base, long int maxsize) *b = save2;
if (val != cnt) { - DP (printf + debug ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); + (unsigned int) val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if (cnt == STARTVAL / sizeof (long)) cnt = 0; @@ -1730,9 +1709,8 @@ long int dram_size (long int *base, long int maxsize) * controlling logic happens */ phys_size_t initdram (int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; + ulong realsize, total; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; int nhr, bank_no; @@ -1747,10 +1725,10 @@ phys_size_t initdram (int board_type) printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); + check_dimm (0, &dimmInfo1);
/* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); + check_dimm (1, &dimmInfo2);
memory_map_bank (0, 0, 0); memory_map_bank (1, 0, 0); @@ -1784,7 +1762,6 @@ phys_size_t initdram (int board_type) /* next, size the SDRAM banks */
realsize = total = 0; - check = GB / 4; if (dimmInfo1.numOfModuleBanks > 0) { checkbank[0] = 1; }