18 Mar
2016
18 Mar
'16
4:59 p.m.
On 02/08/2016 09:27 PM, Saksham Jain wrote:
To solve CAAM coherency issue on ls2080a and ls2085a. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures But even if any data in proximity of these structures is read by core, these structures again are fetched in caches.
To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable.
So, this commit makes CAAM transcations as Write Back with Write and Read Allocate.
Please keep line wrap under 72 characters and keep it consistent.
York