The patch fixes a corner case where adding size to DRAM start resulted in a value (1 << 32), which in turn overflew the u32 computation, which resulted in 0 and it therefore prevented correct setup of the MMU tables.
The addition of DRAM bank start and it's size can end up right at the end of the address space in the special case of a machine with enough memory. To prevent this overflow, shift the start and size separately and add them only after they were shifted.
Hopefully, we only have systems in tree which have DRAM size aligned to 1MiB boundary. If not, this patch would break such systems. On the other hand, such system would be broken by design anyway.
Signed-off-by: Marek Vasut marex@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net --- arch/arm/lib/cache-cp15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 5fdfdbf..3e62d58 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -69,7 +69,7 @@ __weak void dram_bank_mmu_setup(int bank)
debug("%s: bank: %d\n", __func__, bank); for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; + i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20); i++) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) set_section_dcache(i, DCACHE_WRITETHROUGH);