David Grab wrote:
But this didn´t solve the problem. Actually i also couldn´t get the TxCLK work on my RGMII Bridge and i don´t know why. The devices are configured as 100 MBit RGMII and receiving packets from network seems to be functioning (EMAC_OCRX Register increments rapidly). I would be appreciated if someone could give me a tip, what i have forgot to do.
Check the SRD_PFC0/1 registers to ensure you have the right mode selected. Also the corresponding disabling of the TRACE and GPIO lines must be done correctly. Its easy to mess this up.
Next double check your RGMII bridge settings. They are pretty easy to decode and verify.
Check that you are NOT running in 440gp compatibility mode. Otherwise you will not get the 3rd UIC controller (doesn't seem to be a problem for you).
Finally, if its your own hardware, check the timing alignment of TXCLK and TXData lines out of the 440gx. The gigabit spec requires a 2ns delay here (but not on the receive path). You either need some 12-16" of tracking, or a digital delay circuit. Or perhaps your PHY has such a circuit built-in but needs to be activated/configured.
-R