Dear Macpaul Lin,
2010/8/5 Macpaul Lin macpaul@andestech.com:
diff --git a/board/AndesTech/adp-ag101/config.mk b/board/AndesTech/adp-ag101/config.mk new file mode 100644 index 0000000..0b95960 --- /dev/null +++ b/board/AndesTech/adp-ag101/config.mk @@ -0,0 +1,42 @@ +# +# Copyright (C) 2010 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com +# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#
+# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus +# +# see http://www.faraday-tech.com/ for more information
+# A320 has 1 bank of 64 MB DRAM +# +# 1000'0000 to 1400'0000 +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# +# we load ourself to 13f8'0000 +# +# download area is 1200'0000
You forgot to modify A320-related descriptions to your board.
+PLATFORM_RELFLAGS += -gdwarf-2 +TEXT_BASE = 0x03200000 +LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds +EXTERN_LIB += $(shell $(CC) -print-file-name=include)/../static/el/libgcc.a diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h new file mode 100644 index 0000000..311593f --- /dev/null +++ b/include/configs/adp-ag101.h @@ -0,0 +1,319 @@ +/*
- Copyright (C) 2010 Andes Technology Corporation
- Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com
- Macpaul Lin, Andes Technology Corporation macpaul@andestech.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#include <asm/arch/ag101.h>
+/*-----------------------------------------------------------------------
- CPU and Board Configuration Options
- */
+#define CONFIG_ADP_AG101P
+#define CONFIG_USE_INTERRUPT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+/*-----------------------------------------------------------------------
- Timer
- */
+/* a320evb: CONFIG_SYS_HZ: 1000
- ag101: CONFIG_SYS_HZ: APB_CLK (ag101 original timer clock frequency)
- CONFIG_SYS_HZ = APB_CLK = SYS_CLK = CONFIG_SYS_CLK_FREQ /2
- the PWM Timer 4 uses a counter of 15625 for 10 ms, so we need
- it to wrap 100 times (total 1562500) to get 1 sec.
- #define CONFIG_HZ 1562500
- 1562500*25=3906250
- */
+#define CONFIG_SYS_HZ APB_CLK /* ag101 original timer clock frequency */
CONFIG_SYS_HZ should be 1000.
http://lists.denx.de/pipermail/u-boot/2009-February/048403.html http://lists.denx.de/pipermail/u-boot/2010-March/069293.html
+#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+/*
- System Clock
- Suggested frequency lists:
- 16000000 -> 16.000000 MHz
- 18432000 -> 18.432000 MHz
- 22118400 -> 22.118400 MHz
- 83000000 -> 83.000000 MHz
- 33000000 -> 33.000000 MHz
- 36864000 -> 36.864000 MHz
- 48000000 -> 48.000000 MHz CONFIG_ADP_AG101
- 40000000 -> 40.000000 MHz CONFIG_ADP_AG101P
- */
+#ifdef CONFIG_ADP_AG101 +#define CONFIG_SYS_CLK_FREQ 48000000 +#endif
+#ifdef CONFIG_ADP_AG101P +#define CONFIG_SYS_CLK_FREQ 39062500 +#endif
+/*
- Use Externel CLOCK or PCLK
- */
+#undef CONFIG_EXT_CLK
+#ifndef CONFIG_EXT_CLK +#define CONFIG_PCLK +#endif
+#ifdef CONFIG_EXT_CLK +#define TIMER_CLOCK 32768 /* EXT_CLK */ +#else +#define TIMER_CLOCK CONFIG_SYS_HZ /* PCLK */ +#endif
+#define TIMER_LOAD_VAL 0xffffffff
+/*-----------------------------------------------------------------------
- Real Time Clock
- */
+#define CONFIG_RTC_FTRTC010
+/*
- Real Time Clock Divider
- RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
- */
+#ifdef CONFIG_ADP_AG101 +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (2*OSC_5MHZ) +#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) +#endif
+#ifdef CONFIG_ADP_AG101P +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (4*OSC_5MHZ) +#define RTC_DIV_COUNT (0.5) /* Why?? */ +#endif
+/*-----------------------------------------------------------------------
- Serial console configuration
- */
+/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 0x99600000 +#define CONFIG_SYS_NS16550_REG_SIZE -4
+#ifdef CONFIG_ADP_AG101 +#define CONFIG_SYS_NS16550_CLK (46080000 * 20) / 25 /* AG101 */ +#endif
+#ifdef CONFIG_ADP_AG101P +#define CONFIG_SYS_NS16550_CLK (18432000 * 20) / 25 /* AG101P */ +#endif
+/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/*-----------------------------------------------------------------------
- Ethernet
- */
+#define CONFIG_NET_MULTI +#define CONFIG_FTMAC100
+#define CONFIG_BOOTDELAY 3
+/*-----------------------------------------------------------------------
- Command line configuration.
- */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING
+/*-----------------------------------------------------------------------
- Miscellaneous configurable options
- */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/*-----------------------------------------------------------------------
- Stack sizes
- The stack sizes are set up in start.S using the settings below
- */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif
+/*-----------------------------------------------------------------------
- Size of malloc() pool
- */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+/*-----------------------------------------------------------------------
- size in bytes reserved for initial data
+*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128
+/*-----------------------------------------------------------------------
- SDRAM controller configuration
- */
+#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
- FTSDMC020_TP0_TRP(1) | \
- FTSDMC020_TP0_TRCD(1) | \
- FTSDMC020_TP0_TRF(3) | \
- FTSDMC020_TP0_TWR(1) | \
- FTSDMC020_TP0_TCL(2))
+#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
- FTSDMC020_TP1_INI_REFT(8) | \
- FTSDMC020_TP1_REF_INTV(0x180))
+#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
- FTSDMC020_BANK_DDW_X16 | \
- FTSDMC020_BANK_DSZ_256M | \
- FTSDMC020_BANK_MBW_32 | \
- FTSDMC020_BANK_SIZE_64M)
+/*-----------------------------------------------------------------------
- Physical Memory Map
- */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
+/*
- Load address and memory test area should agree with
- board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
- */
ditto.
best regards, Po-Yu Chuang