
29 Jan
2016
29 Jan
'16
7:39 a.m.
On Wed, 27 Jan 2016 08:46:11 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
Some armv7 targets are missing a cache line size declaration. In preparation for "arm: cache: Implement cache range check for v7" patch, add these declarations with the appropriate value for the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD albert.u.boot@aribaud.net
Changes in v2:
- fix include/configs/at91-sama5_common.h (Cortex-A5: 32 bytes)
Applied to u-boot-arm/master, adding Tom's Reviewed-by from V1 since there was no change to TI boards in V2.
Amicalement,
--
Albert.