From: Thierry Reding treding@nvidia.com
Most peripherals on Tegra can do DMA only to the lower 32-bit address space, even on 64-bit SoCs. This limitation is typically overcome by the use of an IOMMU. Since the IOMMU is not entirely trivial to set up and serves no other purpose (I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to the lower 32-bit address space for RAM. This ensures that the physical addresses of buffers that are programmed into the various DMA engines are valid and don't alias to lower addresses.
Cc: Tom Warren twarren@nvidia.com Signed-off-by: Thierry Reding treding@nvidia.com --- board/nvidia/common/board.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index d945de456ea2..1134b31791db 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -264,3 +264,19 @@ void pad_init_mmc(struct mmc_host *host) #endif /* T30 */ } #endif /* MMC */ + +#ifdef CONFIG_ARM64 +/* + * Most hardware on 64-bit Tegra is still restricted to DMA to the lower + * 32-bits of the physical address space. Cap the maximum usable RAM area + * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit + * boundary that most devices can address. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + if (gd->ram_top > 0x100000000) + return 0x100000000; + + return gd->ram_top; +} +#endif