+Bin
Hi,
On 26 March 2017 at 05:48, Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Mon, 2017-03-13 at 16:09 +0200, Andy Shevchenko wrote:
On Fri, Mar 3, 2017 at 12:31 PM, Kever Yang <kever.yang@rock-chips.com
wrote: On 02/28/2017 08:04 PM, Andy Shevchenko wrote:
Add a specific serial driver for Intel MID platforms.
It has special fractional divider which can be programmed via UART_PS, UART_MUL, and UART_DIV registers.
The UART clock is calculated as
UART clock = XTAL * UART_MUL / UART_DIVThe baudrate is calculated as
baud rate = UART clock / UART_PS / DLABInitialize fractional divider correctly for Intel Edison platform.
For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and XTAL frequency is 38.4MHz.
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks!
Tom et all, is it forgotten?
Any update on this? Should I do something about?
Probably Bin can apply it - it's a good idea to cc him on x86 stuff. If not let me know and I can pull it in via DM.
Regards, Simon