This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/mach-imx/mx6/Kconfig | 1 - board/tbs/tbs2910/Kconfig | 18 -- board/tbs/tbs2910/MAINTAINERS | 6 - board/tbs/tbs2910/Makefile | 5 - board/tbs/tbs2910/tbs2910.c | 454 ---------------------------------- board/tbs/tbs2910/tbs2910.cfg | 114 --------- configs/tbs2910_defconfig | 58 ----- include/configs/tbs2910.h | 158 ------------ 8 files changed, 814 deletions(-) delete mode 100644 board/tbs/tbs2910/Kconfig delete mode 100644 board/tbs/tbs2910/MAINTAINERS delete mode 100644 board/tbs/tbs2910/Makefile delete mode 100644 board/tbs/tbs2910/tbs2910.c delete mode 100644 board/tbs/tbs2910/tbs2910.cfg delete mode 100644 configs/tbs2910_defconfig delete mode 100644 include/configs/tbs2910.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9ed827067b1..2b96c55b61b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -559,7 +559,6 @@ source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" -source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri-imx6ull/Kconfig" diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig deleted file mode 100644 index 2e5e1d492a5..00000000000 --- a/board/tbs/tbs2910/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_TBS2910 - -config SYS_BOARD - default "tbs2910" - -config SYS_VENDOR - default "tbs" - -config SYS_CONFIG_NAME - default "tbs2910" - -config MX6Q - default y - -config IMX_CONFIG - default "board/tbs/tbs2910/tbs2910.cfg" - -endif diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS deleted file mode 100644 index bf176553d24..00000000000 --- a/board/tbs/tbs2910/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TBS2910 BOARD -M: Soeren Moch smoch@web.de -S: Maintained -F: board/tbs/tbs2910/ -F: configs/tbs2910_defconfig -F: include/configs/tbs2910.h diff --git a/board/tbs/tbs2910/Makefile b/board/tbs/tbs2910/Makefile deleted file mode 100644 index 78f4a3eecd4..00000000000 --- a/board/tbs/tbs2910/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2014 Soeren Moch smoch@web.de - -obj-y := tbs2910.o diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c deleted file mode 100644 index ecb45f208d0..00000000000 --- a/board/tbs/tbs2910/tbs2910.c +++ /dev/null @@ -1,454 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Soeren Moch smoch@web.de - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/sata.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <i2c.h> -DECLARE_GLOBAL_DATA_PTR; - -#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_SLOW) - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#ifdef CONFIG_SYS_I2C -/* I2C1, SGTL5000 */ -static struct i2c_pads_info i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -/* I2C2 HDMI */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -/* I2C3, CON11, DS1307, PCIe_SMB */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 6) - } -}; -#endif /* CONFIG_SYS_I2C */ - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - /* AR8035 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const pcie_pads[] = { - /* W_DISABLE# */ - MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), - /* PERST# */ - MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int dram_init(void) -{ - gd->ram_size = 2048ul * 1024 * 1024; - return 0; -} - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - /* Reset AR8035 PHY */ - gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); - udelay(500); - gpio_set_value(IMX_GPIO_NR(1, 25), 1); -} - -static void setup_pcie(void) -{ - imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); -} - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); -} - -#ifdef CONFIG_FSL_ESDHC -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - /* - * (U-Boot device node) (Physical Port) - * mmc0 SD2 - * mmc1 SD3 - * mmc2 eMMC - */ - int i, ret; - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - return 0; -} - -/* set environment device to boot device when booting from SD */ -int board_mmc_get_env_dev(int devno) -{ - return devno - 1; -} - -int board_mmc_get_env_part(int devno) -{ - return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */ -} -#endif /* CONFIG_FSL_ESDHC */ - -#ifdef CONFIG_VIDEO_IPUV3 -static void do_enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - /* 1024x768@60Hz (VESA)*/ - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15384, - .left_margin = 160, - .right_margin = 24, - .upper_margin = 29, - .lower_margin = 3, - .hsync_len = 136, - .vsync_len = 6, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} } }; -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - s32 timeout = 100000; - - enable_ipu_clock(); - imx_setup_hdmi(); - - /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); - reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); - writel(reg, &ccm->analog_pll_video); - - writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); - writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); - - reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - while (timeout--) - if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) - break; - if (timeout < 0) - printf("Warning: video pll lock timeout!\n"); - - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_ENABLE; - reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; - writel(reg, &ccm->analog_pll_video); - - /* gate ipu1_di0_clk */ - reg = readl(&ccm->CCGR3); - reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK; - writel(reg, &ccm->CCGR3); - - /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ - reg = readl(&ccm->chsccdr); - reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | - MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | - (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | - (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - writel(reg, &ccm->chsccdr); - - /* enable ipu1_di0_clk */ - reg = readl(&ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; - writel(reg, &ccm->CCGR3); -} -#endif /* CONFIG_VIDEO_IPUV3 */ - -static int ar8035_phy_fixup(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - ar8035_phy_fixup(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - setup_pcie(); - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, - /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -#ifdef CONFIG_USB_EHCI_MX6 -static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - -#ifdef CONFIG_VIDEO_IPUV3 - setup_display(); -#endif -#ifdef CONFIG_SYS_I2C - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -#endif -#ifdef CONFIG_DWC_AHSATA - setup_sata(); -#endif -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif -#ifdef CONFIG_USB_EHCI_MX6 - imx_iomux_v3_setup_multiple_pads( - usb_otg_pads, ARRAY_SIZE(usb_otg_pads)); -#endif - return 0; -} - -int checkboard(void) -{ - puts("Board: TBS2910 Matrix ARM mini PC\n"); - return 0; -} diff --git a/board/tbs/tbs2910/tbs2910.cfg b/board/tbs/tbs2910/tbs2910.cfg deleted file mode 100644 index 3ca807b3157..00000000000 --- a/board/tbs/tbs2910/tbs2910.cfg +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Soeren Moch smoch@web.de - */ - -#define __ASSEMBLY__ -#include "asm/arch/crm_regs.h" -#include "asm/arch/iomux.h" -#include "asm/arch/mx6-ddr.h" - -/* image version 2 for imx6 */ -IMAGE_VERSION 2 -BOOT_FROM sd - -/* set the default clock gates to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF -/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */ -DATA 4, CCM_CCOSR, 0x000000fb - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x77177717 -DATA 4, MX6_IOMUXC_GPR7, 0x77177717 - - -/* - * DDR3/DDR3L settings - * use default 40 Ohm pad drive strength, no odt - * 4x256Mx16 DDR3L-1066 7-7-7 - */ - -/* disable dq pullup */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -/* disable dqs pullup */ -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 -/* set ddr input mode for dq signals */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* set ddr input mode for dqs signals */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* set pad calibration type to DDR3 */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -/* dqs write delay */ -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f -/* dqs read delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 -/* dqs read gating control */ -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300 -/* start delay line calibration */ -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */ -DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974 -/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */ -DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 -/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */ -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */ -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */ -DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 -/* ODT timing */ -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -/* read odt settings, 120 Ohm */ -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 -/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */ -DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 -/* interleaved bank access (row/bank/col), 5 cycles additional read delay */ -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -/* 2GiByte RAM at cs0 */ -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 -/* load mode registers of external ddr chips */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -/* externel chip ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -/* configure and start refreshes, 8 refresh commands at 32 kHz */ -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 -/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -/* set automatic self refresh */ -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -/* controller configuration finished */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig deleted file mode 100644 index 55cd9bd998f..00000000000 --- a/configs/tbs2910_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_THUMB_BUILD=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_TBS2910=y -CONFIG_CMD_HDMIDETECT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_BOOTDELAY=3 -CONFIG_PRE_CONSOLE_BUFFER=y -CONFIG_PRE_CON_BUF_ADDR=0x7c000000 -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="Matrix U-Boot> " -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_EFI_PARTITION=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_DM=y -CONFIG_DWC_AHSATA=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_DM_THERMAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="TBS" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h deleted file mode 100644 index a60223c6235..00000000000 --- a/include/configs/tbs2910.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Soeren Moch smoch@web.de - * - * Configuration settings for the TBS2910 MatrixARM board. - */ - -#ifndef __TBS2910_CONFIG_H -#define __TBS2910_CONFIG_H - -#include "mx6_common.h" - -/* General configuration */ - -#define CONFIG_MACH_TYPE 3980 - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_IMX_THERMAL - -/* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) - -#define CONFIG_SYS_BOOTMAPSZ 0x10000000 - -/* Serial console */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ - -/* Filesystems / image support */ - -/* MMC */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 -#define CONFIG_PHY_ATHEROS - -/* Framebuffer */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_IPUV3 -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP -#endif - -/* PCI */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#endif - -/* SATA */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#ifdef CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USBD_HS -#endif /* CONFIG_CMD_USB_MASS_STORAGE */ -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_PREBOOT \ - "usb start; " \ - "if hdmidet; then " \ - "run set_con_hdmi; " \ - "else " \ - "run set_con_serial; " \ - "fi;" -#endif /* CONFIG_USB_KEYBOARD */ -#endif /* CONFIG_CMD_USB */ - -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1307 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#endif - -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_I2C_EDID -#endif - -/* Environment organization */ -#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */ -#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */ -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (384 * 1024) -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ - "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ - "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ - "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \ - "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \ - "${bootargs_mmc3}\0" \ - "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ - "rdinit=/sbin/init enable_wait_mode=off\0" \ - "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ - "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \ - "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ - "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ - "run bootargs_upd; " \ - "bootm 0x10800000 0x10d00000\0" \ - "console=ttymxc0\0" \ - "fan=gpio set 92\0" \ - "set_con_serial=setenv stdout serial; " \ - "setenv stderr serial;\0" \ - "set_con_hdmi=setenv stdout serial,vga; " \ - "setenv stderr serial,vga;\0" \ - "stderr=serial,vga;\0" \ - "stdin=serial,usbkbd;\0" \ - "stdout=serial,vga;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "if run bootcmd_up1; then " \ - "run bootcmd_up2; " \ - "else " \ - "run bootcmd_mmc; " \ - "fi" - -#endif /* __TBS2910_CONFIG_H * */