Add a clock driver for the MPC83xx architecture.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v1 -> v2: * Added binding of sysreset driver
--- arch/powerpc/cpu/mpc83xx/speed.c | 4 + arch/powerpc/include/asm/config.h | 2 +- drivers/clk/Kconfig | 6 + drivers/clk/Makefile | 1 + drivers/clk/mpc83xx_clk.c | 430 ++++++++++++++++++++++++++++++++++ drivers/clk/mpc83xx_clk.h | 115 +++++++++ include/dt-bindings/clk/mpc83xx-clk.h | 27 +++ 7 files changed, 584 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/mpc83xx_clk.c create mode 100644 drivers/clk/mpc83xx_clk.h create mode 100644 include/dt-bindings/clk/mpc83xx-clk.h
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 5498c19e25..c9bdec0bc0 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -7,6 +7,8 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#ifndef CONFIG_CLK_MPC83XX + #include <common.h> #include <mpc83xx.h> #include <command.h> @@ -591,3 +593,5 @@ U_BOOT_CMD(clocks, 1, 0, do_clocks, "print clock configuration", " clocks" ); + +#endif diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 39eeb39901..d9dfb670af 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -79,7 +79,7 @@ /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO
-#if defined(CONFIG_DM_SERIAL) +#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX) /* * TODO: Convert this to a clock driver exists that can give us the UART * clock here. diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c382e8865f..787c061e44 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -89,4 +89,10 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/renesas/Kconfig"
+config CLK_MPC83XX + bool "Enable MPC83xx clock driver" + depends on CLK + help + Support for the clock driver of the MPC83xx series of SoCs. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e05c607223..67da125669 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o +obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c new file mode 100644 index 0000000000..96f762bfe1 --- /dev/null +++ b/drivers/clk/mpc83xx_clk.c @@ -0,0 +1,430 @@ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <dt-bindings/clk/mpc83xx-clk.h> + +#include "mpc83xx_clk.h" + +DECLARE_GLOBAL_DATA_PTR; + +static u32 *speed; + +struct mpc83xx_clk_priv { + u32 *speed; +}; + +static const char * const names[] = { + [MPC83XX_CLK_CORE] = "Core", + [MPC83XX_CLK_CSB] = "Coherent System Bus", + [MPC83XX_CLK_QE] = "QE", + [MPC83XX_CLK_BRG] = "BRG", + [MPC83XX_CLK_LBIU] = "Local Bus Controller", + [MPC83XX_CLK_LCLK] = "Local Bus", + [MPC83XX_CLK_MEM] = "DDR", + [MPC83XX_CLK_MEM_SEC] = "DDR Secondary", + [MPC83XX_CLK_ENC] = "SEC", + [MPC83XX_CLK_I2C1] = "I2C1", + [MPC83XX_CLK_I2C2] = "I2C2", + [MPC83XX_CLK_TDM] = "TDM", + [MPC83XX_CLK_SDHC] = "SDHC", + [MPC83XX_CLK_TSEC1] = "TSEC1", + [MPC83XX_CLK_TSEC2] = "TSEC2", + [MPC83XX_CLK_USBDR] = "USB DR", + [MPC83XX_CLK_USBMPH] = "USB MPH", + [MPC83XX_CLK_PCIEXP1] = "PCIEXP1", + [MPC83XX_CLK_PCIEXP2] = "PCIEXP2", + [MPC83XX_CLK_SATA] = "SATA", + [MPC83XX_CLK_DMAC] = "DMAC", + [MPC83XX_CLK_PCI] = "PCI", +}; + +struct clk_mode { + u8 low; + u8 high; + int type; +}; + +const struct clk_mode modes[] = { + + [MPC83XX_CLK_CORE] = {0, 0, TYPE_SPECIAL}, + [MPC83XX_CLK_CSB] = {0, 0, TYPE_SPECIAL}, + [MPC83XX_CLK_QE] = {0, 0, TYPE_SPECIAL}, + [MPC83XX_CLK_BRG] = {0, 0, TYPE_SPECIAL}, + [MPC83XX_CLK_MEM] = {1, 1, TYPE_SPMR_DIRECT_MULTIPLY }, + [MPC83XX_CLK_LBIU] = {0, 0, TYPE_SPMR_DIRECT_MULTIPLY }, + [MPC83XX_CLK_LCLK] = {0, 0, TYPE_SPECIAL}, + [MPC83XX_CLK_MEM_SEC] = {0, 0, TYPE_SPMR_DIRECT_MULTIPLY }, /* The same as LBIU */ +#ifndef CONFIG_MPC8313 + [MPC83XX_CLK_TSEC1] = {0, 1, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_TSEC2] = {2, 3, TYPE_SCCR_STANDARD }, +#else + [MPC83XX_CLK_TSEC1] = {0, 1, TYPE_SCCR_STANDARD }, /* FIXME: This has separate enable/disable bit! */ + [MPC83XX_CLK_TSEC2] = {0, 1, TYPE_SCCR_STANDARD }, /* FIXME: This has separate enable/disable bit! */ +#endif + [MPC83XX_CLK_SDHC] = {4, 5, TYPE_SCCR_STANDARD }, +#ifdef CONFIG_MPC834x + [MPC83XX_CLK_ENC] = {6, 7, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_I2C1] = {2, 3, TYPE_SCCR_STANDARD }, /* I2C and TSEC2 are the same register */ +#else + [MPC83XX_CLK_ENC] = {6, 7, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_I2C1] = {6, 7, TYPE_SCCR_STANDARD }, /* I2C and ENC are the same register */ +#endif + [MPC83XX_CLK_I2C2] = {0, 0, TYPE_SPECIAL }, + [MPC83XX_CLK_PCIEXP1] = {10, 11, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_PCIEXP2] = {12, 13, TYPE_SCCR_STANDARD }, +#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC834x) + [MPC83XX_CLK_USBDR] = {10, 11, TYPE_SCCR_STANDARD }, +#else + [MPC83XX_CLK_USBDR] = {8, 9, TYPE_SCCR_STANDARD }, +#endif + [MPC83XX_CLK_USBMPH] = {8, 9, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_PCI] = {15, 15, TYPE_SCCR_ONOFF }, +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8309) + [MPC83XX_CLK_DMAC] = {26, 27, TYPE_SCCR_STANDARD }, +#endif +#if 0 +/* FIXME: All SATA controllers must have the same clock ratio */ +#ifdef CONFIG_MPC83XX_SATA_SUPPORT +#ifdef CONFIG_MPC8379 + [MPC83XX_CLK_SATA] = {24, 25, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_SATA] = {26, 27, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_SATA] = {28, 29, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_SATA] = {30, 31, TYPE_SCCR_STANDARD }, +#else + [MPC83XX_CLK_SATA] = {18, 19, TYPE_SCCR_STANDARD }, + [MPC83XX_CLK_SATA] = {20, 21, TYPE_SCCR_STANDARD }, +#endif +#endif +#endif + [MPC83XX_CLK_TDM] = {26, 27, TYPE_SCCR_STANDARD }, +}; + +int get_clocks(void) +{ + return 0; +} + +inline bool is_clk_valid(int id) +{ + switch (id) { + case MPC83XX_CLK_MEM: +#if defined(CONFIG_MPC8360) + case MPC83XX_CLK_MEM_SEC: +#endif +#ifndef CONFIG_MPC830x + case MPC83XX_CLK_ENC: +#endif + case MPC83XX_CLK_I2C1: +#ifdef CONFIG_MPC8315 + case MPC83XX_CLK_TDM: +#endif +#ifdef CONFIG_MPC83XX_SDHC_SUPPORT + case MPC83XX_CLK_SDHC: +#endif +#ifdef CONFIG_MPC83XX_TSEC1_SUPPORT + case MPC83XX_CLK_TSEC1: +#endif +#ifdef CONFIG_MPC83XX_TSEC2_SUPPORT + case MPC83XX_CLK_TSEC2: +#endif +#if !defined(CONFIG_MPC8360) + case MPC83XX_CLK_USBDR: +#endif +#ifdef CONFIG_MPC834x + case MPC83XX_CLK_USBMPH: +#endif +#ifdef CONFIG_MPC83XX_PCIE1_SUPPORT + case MPC83XX_CLK_PCIEXP1: +#endif +#ifdef CONFIG_MPC83XX_PCIE2_SUPPORT + case MPC83XX_CLK_PCIEXP2: +#endif +#ifdef CONFIG_MPC83XX_SATA_SUPPORT + case MPC83XX_CLK_SATA: +#endif +#ifdef CONFIG_MPC830x + case MPC83XX_CLK_DMAC: +#endif +#ifdef CONFIG_MPC83XX_PCI_SUPPORT + case MPC83XX_CLK_PCI: +#endif + case MPC83XX_CLK_CSB: +#ifdef CONFIG_MPC83XX_SECOND_I2C_SUPPORT + case MPC83XX_CLK_I2C2: +#endif +#if defined(CONFIG_MPC83XX_QUICC_ENGINE) && !defined(CONFIG_MPC8309) + case MPC83XX_CLK_QE: + case MPC83XX_CLK_BRG: +#endif + case MPC83XX_CLK_LCLK: + case MPC83XX_CLK_LBIU: + case MPC83XX_CLK_CORE: + return true; + } + + return false; +} + +static int mpc83xx_clk_request(struct clk *clock) +{ + /* Reject requests of clocks that are not available */ + if (is_clk_valid(clock->id)) + return 0; + else + return -ENODEV; +} + +static inline void init_clks(u32 *speed) +{ + int i; + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 csb_clk = get_csb_clk(im); + + for (i = 0; i < MPC83XX_CLK_COUNT; i++) { + struct clk_mode mode = modes[i]; + ulong mask; + + if (mode.type == TYPE_INVALID) + continue; + + if (mode.type == TYPE_SCCR_STANDARD) { + mask = GENMASK(31 - mode.low, 31 - mode.high); + + switch (sccr_field(im, mask, 31 - mode.high)) { + case 0: + speed[i] = 0; + break; + case 1: + speed[i] = csb_clk; + break; + case 2: + speed[i] = csb_clk / 2; + break; + case 3: + speed[i] = csb_clk / 3; + break; + default: + speed[i] = 0; + } + + continue; + } + + if (mode.type == TYPE_SPMR_DIRECT_MULTIPLY) { + mask = GENMASK(31 - mode.low, 31 - mode.high); + + speed[i] = csb_clk * (1 + sccr_field(im, mask, 31 - mode.high)); + continue; + } + + if (i == MPC83XX_CLK_CSB || i == MPC83XX_CLK_I2C2) { + speed[i] = csb_clk; /* i2c-2 clk is equal to csb clk */ + continue; + } + + if (i == MPC83XX_CLK_QE || i == MPC83XX_CLK_BRG) { + u32 pci_sync_in = get_pci_sync_in(im); + u32 qepmf = spmr_field(im, SPMR_CEPMF, SPMR_CEPMF_SHIFT); + u32 qepdf = spmr_field(im, SPMR_CEPDF, SPMR_CEPDF_SHIFT); + u32 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); + + if (i == MPC83XX_CLK_QE) + speed[i] = qe_clk; + else + speed[i] = qe_clk / 2; + + continue; + } + + if (i == MPC83XX_CLK_LCLK || i == MPC83XX_CLK_LBIU) { + u32 lbiu_clk = csb_clk * + (1 + spmr_field(im, SPMR_LBIUCM, SPMR_LBIUCM_SHIFT)); + u32 clkdiv = lcrr_field(im, LCRR_CLKDIV, LCRR_CLKDIV_SHIFT); + + if (i == MPC83XX_CLK_LBIU) + speed[i] = lbiu_clk; + + switch (clkdiv) { + case 2: + case 4: + case 8: + speed[i] = lbiu_clk / clkdiv; + break; + default: + /* unknown lcrr */ + speed[i] = 0; + } + + continue; + } + + if (i == MPC83XX_CLK_CORE) { + u8 corepll = spmr_field(im, SPMR_COREPLL, SPMR_COREPLL_SHIFT); + u32 corecnf_tab_index = ((corepll & 0x1F) << 2) | + ((corepll & 0x60) >> 5); + + if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) { + /* corecnf_tab_index is too high, possibly wrong value */ + speed[i] = 0; + } + + switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { + case _byp: + case _x1: + case _1x: + speed[i] = csb_clk; + break; + case _1_5x: + speed[i] = (3 * csb_clk) / 2; + break; + case _2x: + speed[i] = 2 * csb_clk; + break; + case _2_5x: + speed[i] = (5 * csb_clk) / 2; + break; + case _3x: + speed[i] = 3 * csb_clk; + break; + default: + /* unknown core to csb ratio */ + speed[i] = 0; + } + + continue; + } + } +} + +static ulong mpc83xx_clk_get_rate(struct clk *clk) +{ + struct mpc83xx_clk_priv *priv = dev_get_priv(clk->dev); + + return priv->speed[clk->id]; +} + +int get_serial_clock(void) +{ + return speed[MPC83XX_CLK_CSB]; +} + +const struct clk_ops mpc83xx_clk_ops = { + .request = mpc83xx_clk_request, + .get_rate = mpc83xx_clk_get_rate, +}; + +static const struct udevice_id mpc83xx_clk_match[] = { + { .compatible = "fsl,mpc83xx-clk", }, + { /* sentinel */ } +}; + +static int mpc83xx_clk_probe(struct udevice *dev) +{ + struct mpc83xx_clk_priv *priv = dev_get_priv(dev); + + speed = malloc((MPC83XX_CLK_COUNT + 1) * sizeof(u32)); + priv->speed = speed; + init_clks(priv->speed); + + gd->arch.csb_clk = speed[MPC83XX_CLK_CSB]; +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) + gd->arch.tsec1_clk = speed[MPC83XX_CLK_TSEC1]; + gd->arch.tsec2_clk = speed[MPC83XX_CLK_TSEC2]; + gd->arch.usbdr_clk = speed[MPC83XX_CLK_USBDR]; +#elif defined(CONFIG_MPC8309) + gd->arch.usbdr_clk = speed[MPC83XX_CLK_USBDR]; +#endif +#if defined(CONFIG_MPC834x) + gd->arch.usbmph_clk = speed[MPC83XX_CLK_USBMPH]; +#endif +#if defined(CONFIG_MPC8315) + gd->arch.tdm_clk = speed[MPC83XX_CLK_TDM]; +#endif +#if defined(CONFIG_FSL_ESDHC) + gd->arch.sdhc_clk = speed[MPC83XX_CLK_SDHC]; +#endif + gd->arch.core_clk = speed[MPC83XX_CLK_CORE]; + gd->arch.i2c1_clk = speed[MPC83XX_CLK_I2C1]; +#if !defined(CONFIG_MPC832x) + gd->arch.i2c2_clk = speed[MPC83XX_CLK_I2C2]; +#endif +#if !defined(CONFIG_MPC8309) + gd->arch.enc_clk = speed[MPC83XX_CLK_ENC]; +#endif + gd->arch.lbiu_clk = speed[MPC83XX_CLK_LBIU]; + gd->arch.lclk_clk = speed[MPC83XX_CLK_LCLK]; + gd->mem_clk = speed[MPC83XX_CLK_MEM]; +#if defined(CONFIG_MPC8360) + gd->arch.mem_sec_clk = speed[MPC83XX_CLK_MEM_SEC]; +#endif +#if defined(CONFIG_QE) + gd->arch.qe_clk = speed[MPC83XX_CLK_QE]; + gd->arch.brg_clk = speed[MPC83XX_CLK_BRG]; +#endif +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) + gd->arch.pciexp1_clk = speed[MPC83XX_CLK_PCIEXP1]; + gd->arch.pciexp2_clk = speed[MPC83XX_CLK_PCIEXP2]; +#endif +#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) + gd->arch.sata_clk = speed[MPC83XX_CLK_SATA]; +#endif + gd->pci_clk = speed[MPC83XX_CLK_PCI]; + gd->cpu_clk = speed[MPC83XX_CLK_CORE]; + gd->bus_clk = speed[MPC83XX_CLK_CSB]; + + return 0; +} + +static int mpc83xx_clk_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + + ret = device_bind_driver(dev, "mpc83xx_sysreset", "sysreset", + &sys_child); + if (ret) + debug("Warning: No sysreset driver: ret=%d\n", ret); + + return 0; +} + +U_BOOT_DRIVER(mpc83xx_clk) = { + .name = "mpc83xx_clk", + .id = UCLASS_CLK, + .of_match = mpc83xx_clk_match, + .ops = &mpc83xx_clk_ops, + .probe = mpc83xx_clk_probe, + .priv_auto_alloc_size = sizeof(struct mpc83xx_clk_priv), + .bind = mpc83xx_clk_bind, +}; + +static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + char buf[32]; + + for (i = 0; i < MPC83XX_CLK_COUNT; i++) { + if (!is_clk_valid(i)) + continue; + + printf("%s = %s MHz\n", names[i], strmhz(buf, speed[i])); + } + + return 0; +} + +U_BOOT_CMD( + clocks, 1, 1, do_clocks, + "display values of SoC's clocks", + "" +); diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h new file mode 100644 index 0000000000..75db2f3699 --- /dev/null +++ b/drivers/clk/mpc83xx_clk.h @@ -0,0 +1,115 @@ +enum { + _unk, + _off, + _byp, + _x8, + _x4, + _x2, + _x1, + _1x, + _1_5x, + _2x, + _2_5x, + _3x +}; + +struct corecnf { + int core_csb_ratio; + int vco_divider; +}; + +static struct corecnf corecnf_tab[] = { + {_byp, _byp}, /* 0x00 */ + {_byp, _byp}, /* 0x01 */ + {_byp, _byp}, /* 0x02 */ + {_byp, _byp}, /* 0x03 */ + {_byp, _byp}, /* 0x04 */ + {_byp, _byp}, /* 0x05 */ + {_byp, _byp}, /* 0x06 */ + {_byp, _byp}, /* 0x07 */ + {_1x, _x2}, /* 0x08 */ + {_1x, _x4}, /* 0x09 */ + {_1x, _x8}, /* 0x0A */ + {_1x, _x8}, /* 0x0B */ + {_1_5x, _x2}, /* 0x0C */ + {_1_5x, _x4}, /* 0x0D */ + {_1_5x, _x8}, /* 0x0E */ + {_1_5x, _x8}, /* 0x0F */ + {_2x, _x2}, /* 0x10 */ + {_2x, _x4}, /* 0x11 */ + {_2x, _x8}, /* 0x12 */ + {_2x, _x8}, /* 0x13 */ + {_2_5x, _x2}, /* 0x14 */ + {_2_5x, _x4}, /* 0x15 */ + {_2_5x, _x8}, /* 0x16 */ + {_2_5x, _x8}, /* 0x17 */ + {_3x, _x2}, /* 0x18 */ + {_3x, _x4}, /* 0x19 */ + {_3x, _x8}, /* 0x1A */ + {_3x, _x8}, /* 0x1B */ +}; + +enum reg_type { + REG_SCCR, + REG_SPMR, +}; + +enum mode_type { + TYPE_INVALID = 0, + TYPE_SCCR_STANDARD, + TYPE_SCCR_ONOFF, + TYPE_SPMR_DIRECT_MULTIPLY, + TYPE_SPECIAL, +}; + +static inline u32 get_spmr(immap_t *im) +{ + u32 res = in_be32(&im->clk.spmr); + + return res; +} + +static inline u32 get_sccr(immap_t *im) +{ + u32 res = in_be32(&im->clk.sccr); + + return res; +} + +static inline u32 get_lcrr(immap_t *im) +{ + u32 res = in_be32(&im->im_lbc.lcrr); + + return res; +} + +static inline u32 get_pci_sync_in(immap_t *im) +{ + u8 clkin_div; + + clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT; + return CONFIG_SYS_CLK_FREQ / (1 + clkin_div); +} + +static inline u32 get_csb_clk(immap_t *im) +{ + u8 spmf; + + spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + return CONFIG_SYS_CLK_FREQ * spmf; +} + +static inline uint spmr_field(immap_t *im, u32 mask, uint shift) +{ + return (get_spmr(im) & mask) >> shift; +} + +static inline uint sccr_field(immap_t *im, u32 mask, uint shift) +{ + return (get_sccr(im) & mask) >> shift; +} + +static inline uint lcrr_field(immap_t *im, u32 mask, uint shift) +{ + return (get_lcrr(im) & mask) >> shift; +} diff --git a/include/dt-bindings/clk/mpc83xx-clk.h b/include/dt-bindings/clk/mpc83xx-clk.h new file mode 100644 index 0000000000..3e5b2858c0 --- /dev/null +++ b/include/dt-bindings/clk/mpc83xx-clk.h @@ -0,0 +1,27 @@ +#ifndef DT_BINDINGS_MPC83XX_CLK_H +#define DT_BINDINGS_MPC83XX_CLK_H +#define MPC83XX_CLK_CORE 0 +#define MPC83XX_CLK_CSB 1 +#define MPC83XX_CLK_QE 2 +#define MPC83XX_CLK_BRG 3 +#define MPC83XX_CLK_LBIU 4 +#define MPC83XX_CLK_LCLK 5 +#define MPC83XX_CLK_MEM 6 +#define MPC83XX_CLK_MEM_SEC 7 +#define MPC83XX_CLK_ENC 8 +#define MPC83XX_CLK_I2C1 9 +#define MPC83XX_CLK_I2C2 10 +#define MPC83XX_CLK_TDM 11 +#define MPC83XX_CLK_SDHC 12 +#define MPC83XX_CLK_TSEC1 13 +#define MPC83XX_CLK_TSEC2 14 +#define MPC83XX_CLK_USBDR 15 +#define MPC83XX_CLK_USBMPH 16 +#define MPC83XX_CLK_PCIEXP1 17 +#define MPC83XX_CLK_PCIEXP2 18 +#define MPC83XX_CLK_SATA 19 +#define MPC83XX_CLK_DMAC 20 +#define MPC83XX_CLK_PCI 21 +/* Count */ +#define MPC83XX_CLK_COUNT 22 +#endif /* DT_BINDINGS_MPC83XX_CLK_H */ -- 2.16.1