Hi Jerry,
On Thursday, 2. March 2006 04:43, Jerry K. Schieffer wrote:
Thank you for your help. In answer to your questions:
Can you "see" the PCI IDE controller at this address? What's the
output of:
=> md.b e80001f0 10
I believe not because => md.b e8000000 10 e8000000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
Correct. That's _not_ the IDE controller.
Found PCI device 00.04.00: vendor ID = 0x105a device ID = 0x0d30 command register = 0x0004
Hmmm. I/O access is not enabled. So any access to the I/O spaces will fail.
status register = 0x0210 revision ID = 0x02 class code = 0x01 (Mass storage controller) sub class code = 0x01 programming interface = 0x8a cache line = 0x00 latency time = 0x40 header type = 0x00 BIST = 0x00 base address 0 = 0x000001f1
Also strange. I would expect the BAR's to be assigned to something like:
base address 0 = 0x008001f1
Then you could access this I/O space at 0xe88001f0. Here a dump from our Walnut with a PCI IDE controller:
Found PCI device 00.01.00: vendor ID = 0x1191 device ID = 0x0009 command register = 0x0007 status register = 0x02b0 revision ID = 0x10 class code = 0x01 (Mass storage controller) sub class code = 0x80 programming interface = 0x00 cache line = 0x08 latency time = 0x80 header type = 0x00 BIST = 0x00 base address 0 = 0x00800001 base address 1 = 0x00800009 base address 2 = 0x00800011 base address 3 = 0x00800019 base address 4 = 0x00800081 base address 5 = 0x80000000 cardBus CIS pointer = 0x00000000 sub system vendor ID = 0x1191 sub system ID = 0x0009 expansion ROM base address = 0x40000000 interrupt line = 0x1e interrupt pin = 0x01 min Grant = 0x0b max Latency = 0x04 => md.b e8800010 10 e8800010: 7f 7f 7f 7f 7f 7f 7f 7f ff ff 7f ff ff ff ff ff ................
Do you use the same PCI config setup as the Walnut in your board config file? Do you use the lastest U-Boot version (current GIT or CVS version)?
Best regards, Stefan