Signed-off-by: Joe Hershberger joe.hershberger@ni.com Cc: Joe Hershberger joe.hershberger@gmail.com Cc: Kim Phillips kim.phillips@freescale.com --- Changes for v2: - Split
include/configs/MPC8315ERDB.h | 13 +++++++------ include/configs/MPC8323ERDB.h | 6 +++--- include/configs/MPC832XEMDS.h | 6 +++--- include/configs/MPC8349EMDS.h | 36 ++++++++++++++++++------------------ include/configs/MPC8360EMDS.h | 32 ++++++++++++++++---------------- include/configs/MPC8360ERDK.h | 8 ++++---- include/configs/MPC837XEMDS.h | 12 ++++++------ include/configs/MPC837XERDB.h | 8 ++++---- include/configs/mpc8308_p1m.h | 2 +- include/configs/tuxa1.h | 2 +- include/configs/ve8313.h | 36 ++++++++++++++++++------------------ 11 files changed, 81 insertions(+), 80 deletions(-)
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index a0cfd00..cffb9ff 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -268,13 +268,14 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 4d4c758..6766b76 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -62,7 +62,7 @@ /* * IMMR new address */ -#define CONFIG_SYS_IMMR 0xE0000000 +#define CONFIG_SYS_IMMR 0xE0000000
/* * System performance @@ -177,9 +177,9 @@ * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ +#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f136a8e..0342194 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -185,9 +185,9 @@ #undef CONFIG_SYS_FLASH_CHECKSUM
/* - * BCSR on the Local Bus + * Status buffer (BCSR) on the Local Bus */ -#define CONFIG_SYS_BCSR 0xF8000000 +#define CONFIG_SYS_BCSR 0xF8000000 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
@@ -251,7 +251,7 @@ #endif
/* - * Windows to access PIB via local bus + * Windows to access Platform I/O Boards (PIB) via local bus */ #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 45b6b5f..b238880 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -113,24 +113,24 @@ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ #if defined(CONFIG_DDR_II) #define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 #define CONFIG_SYS_DDR_MODE 0x47d00432 #define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #else #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ +#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
#if defined(CONFIG_DDR_32BIT) /* set burst length to 8 for 32-bit data path */ @@ -143,12 +143,6 @@ #endif
/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ @@ -185,7 +179,7 @@ /* * BCSR register on local bus 32KB, 8-bit wide for MDS config reg */ -#define CONFIG_SYS_BCSR 0xE2400000 +#define CONFIG_SYS_BCSR 0xE2400000 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ @@ -209,7 +203,7 @@ */ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_SYS_LBC_LBCR 0x00000000
/* * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. @@ -217,6 +211,12 @@ */ #undef CONFIG_SYS_LB_SDRAM
+/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + #ifdef CONFIG_SYS_LB_SDRAM /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ /* diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 49d64a5..8927e2f 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -106,7 +106,7 @@ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */ #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_83XX_DDR_USES_CS0
@@ -131,25 +131,25 @@ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ #if defined(CONFIG_DDR_II) #define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 #define CONFIG_SYS_DDR_MODE 0x47d00432 #define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #else -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) +#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ #define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ +#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ #endif #endif
@@ -195,11 +195,11 @@ * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ @@ -219,7 +219,7 @@ /* * BCSR on the Local Bus */ -#define CONFIG_SYS_BCSR 0xF8000000 +#define CONFIG_SYS_BCSR 0xF8000000 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 851872a..0ad10d4 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -105,14 +105,14 @@ */ #define CONFIG_DDR_II #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) #define CONFIG_SYS_DDR_MODE 0x47800432 #define CONFIG_SYS_DDR_MODE2 0x8000c000
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index abccfd6..325be32 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -223,17 +223,17 @@ */ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 -#define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1
/* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ @@ -262,7 +262,7 @@ /* * BCSR on the Local Bus */ -#define CONFIG_SYS_BCSR 0xF8000000 +#define CONFIG_SYS_BCSR 0xF8000000 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
@@ -272,10 +272,10 @@ /* * NAND Flash on the Local Bus */ -#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_NAND 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index ea3056b..270ad41 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -165,9 +165,9 @@ * Manually set up DDR parameters */ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ @@ -208,8 +208,8 @@ #endif #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0442 << SDRAM_MODE_SD_SHIFT)) - /* 0x04400442 */ /* DDR400 */ + | (0x0442 << SDRAM_MODE_SD_SHIFT)) + /* 0x04400442 */ /* DDR400 */ #define CONFIG_SYS_DDR_MODE2 0x00000000
/* diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index d7a3a96..4c9a766 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -155,7 +155,7 @@
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | 0x00010000 /* ODT_WR to CSn */ \ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h index ceeb5a3..5ce8ad5 100644 --- a/include/configs/tuxa1.h +++ b/include/configs/tuxa1.h @@ -58,7 +58,7 @@ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ BR_V) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index abb57fe..8beac34 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -147,12 +147,12 @@ (2 << BR_PS_SHIFT) | /* 16 bit */ \ BR_V) /* valid */ #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EAD) - /* 0xfe000c55 */ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV4 \ + | OR_GPCM_SCY_5 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EAD) + /* 0xfe000c55 */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ @@ -202,18 +202,18 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ - | BR_PS_8 \ - | BR_DECC_CHK_GEN \ - | BR_MS_FCM \ - | BR_V ) /* valid */ - /* 0x61000c21 */ -#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \ - | OR_FCM_BCTLD \ - | OR_FCM_CHT \ - | OR_FCM_SCY_2 \ - | OR_FCM_RST \ - | OR_FCM_TRLX) - /* 0xffff90ac */ + | BR_PS_8 \ + | BR_DECC_CHK_GEN \ + | BR_MS_FCM \ + | BR_V ) /* valid */ + /* 0x61000c21 */ +#define CONFIG_SYS_NAND_OR_PRELIM ( 0xffff8000 \ + | OR_FCM_BCTLD \ + | OR_FCM_CHT \ + | OR_FCM_SCY_2 \ + | OR_FCM_RST \ + | OR_FCM_TRLX) + /* 0xffff90ac */
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM