TI's J7200 SoC has a single instance of PCIe Controller namely PCIe1 which is a Cadence PCIe Controller. To support PCIe functionality with the PCIe1 instance of PCIe, enable the corresponding configs.
Signed-off-by: Siddharth Vadapalli s-vadapalli@ti.com ---
v2: https://patchwork.ozlabs.org/project/uboot/patch/20241011130258.3452687-3-s-... No changes since v2.
v1: https://patchwork.ozlabs.org/project/uboot/patch/20240821145908.3408573-3-s-... Changes since v1: - Updated j7200_evm_a72_defconfig to enable NVMe configs since NVMe is now supported with this series.
Regards, Siddharth.
configs/j7200_evm_a72_defconfig | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 2fbfda5cf8..12745a9adc 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set +CONFIG_PCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 @@ -71,6 +72,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y @@ -153,6 +155,9 @@ CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83869=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_NVME_PCI=y +CONFIG_PCI_CONFIG_HOST_BRIDGE=y +CONFIG_PCIE_CDNS_TI=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_TORRENT=y