Even the 8bit case needs KBCB configured, as pin D7 is located in this pingroup. Also pingroup ATC seems to come out of reset with config set to NAND, so we need to explictly configure some other function to this group in order to avoid clashing settings.
Signed-off-by: Lucas Stach dev@lynxeye.de --- arch/arm/cpu/tegra20-common/funcmux.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c index a1c55a6..30fdf1c 100644 --- a/arch/arm/cpu/tegra20-common/funcmux.c +++ b/arch/arm/cpu/tegra20-common/funcmux.c @@ -266,17 +266,25 @@ int funcmux_select(enum periph_id id, int config) break; case FUNCMUX_NDFLASH_KBC_8_BIT: pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PINGRP_KBCB, PMUX_FUNC_NAND); pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND); pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND); pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND); pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND);
pinmux_tristate_disable(PINGRP_KBCA); + pinmux_tristate_disable(PINGRP_KBCB); pinmux_tristate_disable(PINGRP_KBCC); pinmux_tristate_disable(PINGRP_KBCD); pinmux_tristate_disable(PINGRP_KBCE); pinmux_tristate_disable(PINGRP_KBCF);
+ /* + * configure pingroup ATC to something unrelated to + * avoid ATC overriding KBC + */ + pinmux_set_func(PINGRP_ATC, PMUX_FUNC_GMI); + bad_config = 0; break; }