This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/Kconfig | 1 - board/freescale/ls1021atwr/Kconfig | 17 - board/freescale/ls1021atwr/MAINTAINERS | 15 - board/freescale/ls1021atwr/Makefile | 9 - board/freescale/ls1021atwr/README | 115 --- board/freescale/ls1021atwr/dcu.c | 46 -- board/freescale/ls1021atwr/ls1021atwr.c | 764 ------------------ board/freescale/ls1021atwr/ls102xa_pbi.cfg | 12 - .../ls1021atwr/ls102xa_rcw_sd_ifc.cfg | 8 - .../ls1021atwr/ls102xa_rcw_sd_qspi.cfg | 8 - board/freescale/ls1021atwr/psci.S | 24 - configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 56 -- configs/ls1021atwr_nor_defconfig | 59 -- configs/ls1021atwr_nor_lpuart_defconfig | 57 -- configs/ls1021atwr_qspi_defconfig | 60 -- ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 70 -- configs/ls1021atwr_sdcard_ifc_defconfig | 67 -- configs/ls1021atwr_sdcard_qspi_defconfig | 70 -- include/configs/ls1021atwr.h | 505 ------------ 19 files changed, 1963 deletions(-) delete mode 100644 board/freescale/ls1021atwr/Kconfig delete mode 100644 board/freescale/ls1021atwr/MAINTAINERS delete mode 100644 board/freescale/ls1021atwr/Makefile delete mode 100644 board/freescale/ls1021atwr/README delete mode 100644 board/freescale/ls1021atwr/dcu.c delete mode 100644 board/freescale/ls1021atwr/ls1021atwr.c delete mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg delete mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg delete mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg delete mode 100644 board/freescale/ls1021atwr/psci.S delete mode 100644 configs/ls1021atwr_nor_SECURE_BOOT_defconfig delete mode 100644 configs/ls1021atwr_nor_defconfig delete mode 100644 configs/ls1021atwr_nor_lpuart_defconfig delete mode 100644 configs/ls1021atwr_qspi_defconfig delete mode 100644 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig delete mode 100644 configs/ls1021atwr_sdcard_ifc_defconfig delete mode 100644 configs/ls1021atwr_sdcard_qspi_defconfig delete mode 100644 include/configs/ls1021atwr.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6cadd96378b..97faf09e916 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1508,7 +1508,6 @@ source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" -source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1021aiot/Kconfig" source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1012aqds/Kconfig" diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig deleted file mode 100644 index a4641cbca09..00000000000 --- a/board/freescale/ls1021atwr/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if TARGET_LS1021ATWR - -config SYS_BOARD - default "ls1021atwr" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "ls102xa" - -config SYS_CONFIG_NAME - default "ls1021atwr" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS deleted file mode 100644 index c8b93c64697..00000000000 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ /dev/null @@ -1,15 +0,0 @@ -LS1021ATWR BOARD -M: Alison Wang alison.wang@nxp.com -S: Maintained -F: board/freescale/ls1021atwr/ -F: include/configs/ls1021atwr.h -F: configs/ls1021atwr_nor_defconfig -F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig -F: configs/ls1021atwr_nor_lpuart_defconfig -F: configs/ls1021atwr_sdcard_ifc_defconfig -F: configs/ls1021atwr_sdcard_qspi_defconfig -F: configs/ls1021atwr_qspi_defconfig - -M: Sumit Garg sumit.garg@nxp.com -S: Maintained -F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile deleted file mode 100644 index d9a2f52f2b6..00000000000 --- a/board/freescale/ls1021atwr/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1021atwr.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README deleted file mode 100644 index 896a6594768..00000000000 --- a/board/freescale/ls1021atwr/README +++ /dev/null @@ -1,115 +0,0 @@ -Overview --------- -The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. - -LS1021A SoC Overview ------------------- -The QorIQ LS1 family, which includes the LS1021A communications processor, -is built on Layerscape architecture, the industry's first software-aware, -core-agnostic networking architecture to offer unprecedented efficiency -and scale. - -A member of the value-performance tier, the QorIQ LS1021A processor provides -extensive integration and power efficiency for fanless, small form factor -enterprise networking applications. Incorporating dual ARM Cortex-A7 cores -running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark -performance of over 6,000, as well as virtualization support, advanced -security features and the broadest array of high-speed interconnects and -optimized peripheral features ever offered in a sub-3 W processor. - -The QorIQ LS1021A processor features an integrated LCD controller, -CAN controller for implementing industrial protocols, DDR3L/4 running -up to 1600 MHz, integrated security engine and QUICC Engine, and ECC -protection on both L1 and L2 caches. The LS1021A processor is pin- and -software-compatible with the QorIQ LS1020A and LS1022A processors. - -The LS1021A SoC includes the following function and features: - - - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture - - Dual high-preformance ARM Cortex-A7 cores, each core includes: - - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) - - 512 Kbyte shared coherent L2 Cache (with ECC protection) - - NEON Co-processor (per core) - - 40-bit physical addressing - - Vector floating-point support - - ARM Core-Link CCI-400 Cache Coherent Interconnect - - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration - supporting speeds up to 1600Mtps - - ECC and interleaving support - - VeTSEC Ethernet complex - - Up to 3x virtualized 10/100/1000 Ethernet controllers - - MII, RMII, RGMII, and SGMII support - - QoS, lossless flow control, and IEEE 1588 support - - 4-lane 6GHz SerDes - - High speed interconnect (4 SerDes lanes with are muxed for these protocol) - - Two PCI Express Gen2 controllers running at up to 5 GHz - - One Serial ATA 3.0 supporting 6 GT/s operation - - Two SGMII interfaces supporting 1000 Mbps - - Additional peripheral interfaces - - One high-speed USB 3.0 controller with integrated PHY and one high-speed - USB 2.00 controller with ULPI - - Integrated flash controller (IFC) with 16-bit interface - - Quad SPI NOR Flash - - One enhanced Secure digital host controller - - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) - - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power - UARTs - - Three I2C controllers - - Eight FlexTimers four supporting PWM and four FlexCAN ports - - Four GPIO controllers supporting up to 109 general purpose I/O signals - - Integrated advanced audio block: - - Four synchronous audio interfaces (SAI) - - Sony/Philips Digital Interconnect Format (SPDIF) - - Asynchronous Sample Rate Converter (ASRC) - - Hardware based crypto offload engine - - IPSec forwarding at up to 1Gbps - - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported - - Public key hardware accelerator - - True Random Number Generator (NIST Certified) - - Advanced Encryption Standard Accelerators (AESA) - - Data Encryption Standard Accelerators - - QUICC Engine ULite block - - Two universal communication controllers (TDM and HDLC) supporting 64 - multichannels, each running at 64 Kbps - - Support for 256 channels of HDLC - - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported - -LS1021ATWR board Overview -------------------------- - - DDR Controller - - Supports rates of up to 1600 MHz data-rate - - Supports one DDR3LP SDRAM. - - IFC/Local Bus - - NOR: 128MB 16-bit NOR Flash - - Ethernet - - Three on-board RGMII 10/100/1G ethernet ports. - - CPLD - - Clocks - - System and DDR clock (SYSCLK, DDRCLK) - - SERDES clocks - - Power Supplies - - SDHC - - SDHC/SDXC connector - - Other IO - - One Serial port - - Three I2C ports - -Memory map ------------ -The addresses in brackets are physical addresses. - -Start Address End Address Description Size -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB - -LS1021a rev1.0 Soc specific Options/Settings --------------------------------------------- -If the LS1021a Soc is rev1.0, you need modify the configure file. -Add the following define in include/configs/ls1021atwr.h: -#define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c deleted file mode 100644 index e1191f134cb..00000000000 --- a/board/freescale/ls1021atwr/dcu.c +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * FSL DCU Framebuffer driver - */ - -#include <common.h> -#include <fsl_dcu_fb.h> -#include "div64.h" -#include "../common/dcu_sii9022a.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long long div; - - div = (unsigned long long)(gd->bus_clk / 1000); - div *= (unsigned long long)pixclock; - do_div(div, 1000000000); - - return div; -} - -int platform_dcu_init(unsigned int xres, unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - const char *name; - unsigned int pixel_format; - - if (strncmp(port, "twr_lcd", 4) == 0) { - name = "TWR_LCD_RGB card"; - } else { - name = "HDMI"; - dcu_set_dvi_encoder(dcu_fb_videomode); - } - - printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - - pixel_format = 32; - fsl_dcu_init(xres, yres, pixel_format); - - return 0; -} diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c deleted file mode 100644 index dcd6d933ea8..00000000000 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ /dev/null @@ -1,764 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <i2c.h> -#include <asm/io.h> -#include <asm/arch/immap_ls102xa.h> -#include <asm/arch/clock.h> -#include <asm/arch/fsl_serdes.h> -#include <asm/arch/ls102xa_devdis.h> -#include <asm/arch/ls102xa_soc.h> -#include <hwconfig.h> -#include <mmc.h> -#include <fsl_csu.h> -#include <fsl_esdhc.h> -#include <fsl_ifc.h> -#include <fsl_immap.h> -#include <netdev.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <fsl_sec.h> -#include <fsl_devdis.h> -#include <spl.h> -#include "../common/sleep.h" -#ifdef CONFIG_U_QE -#include <fsl_qe.h> -#endif -#include <fsl_validate.h> - - -DECLARE_GLOBAL_DATA_PTR; - -#define VERSION_MASK 0x00FF -#define BANK_MASK 0x0001 -#define CONFIG_RESET 0x1 -#define INIT_RESET 0x1 - -#define CPLD_SET_MUX_SERDES 0x20 -#define CPLD_SET_BOOT_BANK 0x40 - -#define BOOT_FROM_UPPER_BANK 0x0 -#define BOOT_FROM_LOWER_BANK 0x1 - -#define LANEB_SATA (0x01) -#define LANEB_SGMII1 (0x02) -#define LANEC_SGMII1 (0x04) -#define LANEC_PCIEX1 (0x08) -#define LANED_PCIEX2 (0x10) -#define LANED_SGMII2 (0x20) - -#define MASK_LANE_B 0x1 -#define MASK_LANE_C 0x2 -#define MASK_LANE_D 0x4 -#define MASK_SGMII 0x8 - -#define KEEP_STATUS 0x0 -#define NEED_RESET 0x1 - -#define SOFT_MUX_ON_I2C3_IFC 0x2 -#define SOFT_MUX_ON_CAN3_USB2 0x8 -#define SOFT_MUX_ON_QE_LCD 0x10 - -#define PIN_I2C3_IFC_MUX_I2C3 0x0 -#define PIN_I2C3_IFC_MUX_IFC 0x1 -#define PIN_CAN3_USB2_MUX_USB2 0x0 -#define PIN_CAN3_USB2_MUX_CAN3 0x1 -#define PIN_QE_LCD_MUX_LCD 0x0 -#define PIN_QE_LCD_MUX_QE 0x1 - -struct cpld_data { - u8 cpld_ver; /* cpld revision */ - u8 cpld_ver_sub; /* cpld sub revision */ - u8 pcba_ver; /* pcb revision number */ - u8 system_rst; /* reset system by cpld */ - u8 soft_mux_on; /* CPLD override physical switches Enable */ - u8 cfg_rcw_src1; /* Reset config word 1 */ - u8 cfg_rcw_src2; /* Reset config word 2 */ - u8 vbank; /* Flash bank selection Control */ - u8 gpio; /* GPIO for TWR-ELEV */ - u8 i2c3_ifc_mux; - u8 mux_spi2; - u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ - u8 qe_lcd_mux; /* QE and LCD Selection */ - u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ - u8 global_rst; /* reset with init CPLD reg to default */ - u8 rev1; /* Reserved */ - u8 rev2; /* Reserved */ -}; - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -static void cpld_show(void) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", - in_8(&cpld_data->cpld_ver) & VERSION_MASK, - in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, - in_8(&cpld_data->pcba_ver) & VERSION_MASK, - in_8(&cpld_data->vbank) & BANK_MASK); - -#ifdef CONFIG_DEBUG - printf("soft_mux_on =%x\n", - in_8(&cpld_data->soft_mux_on)); - printf("cfg_rcw_src1 =%x\n", - in_8(&cpld_data->cfg_rcw_src1)); - printf("cfg_rcw_src2 =%x\n", - in_8(&cpld_data->cfg_rcw_src2)); - printf("vbank =%x\n", - in_8(&cpld_data->vbank)); - printf("gpio =%x\n", - in_8(&cpld_data->gpio)); - printf("i2c3_ifc_mux =%x\n", - in_8(&cpld_data->i2c3_ifc_mux)); - printf("mux_spi2 =%x\n", - in_8(&cpld_data->mux_spi2)); - printf("can3_usb2_mux =%x\n", - in_8(&cpld_data->can3_usb2_mux)); - printf("qe_lcd_mux =%x\n", - in_8(&cpld_data->qe_lcd_mux)); - printf("serdes_mux =%x\n", - in_8(&cpld_data->serdes_mux)); -#endif -} -#endif - -int checkboard(void) -{ - puts("Board: LS1021ATWR\n"); -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - cpld_show(); -#endif - - return 0; -} - -void ddrmc_init(void) -{ - struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; - u32 temp_sdram_cfg, tmp; - - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); - - out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); - - out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); - out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); - out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); - out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); - out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); - out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - out_be32(&ddr->sdram_cfg_2, - DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); - out_be32(&ddr->init_ext_addr, (1 << 31)); - - /* DRAM VRef will not be trained */ - out_be32(&ddr->ddr_cdr2, - DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); - } else -#endif - { - out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); - out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); - } - - out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); - out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); - - out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); - - out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); - - out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); - out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); - - out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); - - out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); - out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); - - out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); - - /* DDR erratum A-009942 */ - tmp = in_be32(&ddr->debug[28]); - out_be32(&ddr->debug[28], tmp | 0x0070006f); - - udelay(1); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - /* enter self-refresh */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); - temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; - out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); - - temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); - } else -#endif - temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); - - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - /* exit self-refresh */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); - temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; - out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); - } -#endif -} - -int dram_init(void) -{ -#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) - ddrmc_init(); -#endif - - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) - fsl_dp_resume(); -#endif - - return 0; -} - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {CONFIG_SYS_FSL_ESDHC_ADDR}, -}; - -int board_mmc_init(bd_t *bis) -{ - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - - return pci_eth_init(bis); -} - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -static void convert_serdes_mux(int type, int need_reset) -{ - char current_serdes; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - current_serdes = cpld_data->serdes_mux; - - switch (type) { - case LANEB_SATA: - current_serdes &= ~MASK_LANE_B; - break; - case LANEB_SGMII1: - current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); - break; - case LANEC_SGMII1: - current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); - break; - case LANED_SGMII2: - current_serdes |= MASK_LANE_D; - break; - case LANEC_PCIEX1: - current_serdes |= MASK_LANE_C; - break; - case (LANED_PCIEX2 | LANEC_PCIEX1): - current_serdes |= MASK_LANE_C; - current_serdes &= ~MASK_LANE_D; - break; - default: - printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); - return; - } - - cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; - cpld_data->serdes_mux = current_serdes; - - if (need_reset == 1) { - printf("Reset board to enable configuration\n"); - cpld_data->system_rst = CONFIG_RESET; - } -} - -int config_serdes_mux(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; - - protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; - switch (protocol) { - case 0x10: - convert_serdes_mux(LANEB_SATA, KEEP_STATUS); - convert_serdes_mux(LANED_PCIEX2 | - LANEC_PCIEX1, KEEP_STATUS); - break; - case 0x20: - convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); - convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); - convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); - break; - case 0x30: - convert_serdes_mux(LANEB_SATA, KEEP_STATUS); - convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); - convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); - break; - case 0x70: - convert_serdes_mux(LANEB_SATA, KEEP_STATUS); - convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); - convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); - break; - } - - return 0; -} -#endif - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -int config_board_mux(void) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - int conflict_flag; - - conflict_flag = 0; - if (hwconfig("i2c3")) { - conflict_flag++; - cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; - cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3; - } - - if (hwconfig("ifc")) { - conflict_flag++; - /* some signals can not enable simultaneous*/ - if (conflict_flag > 1) - goto conflict; - cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; - cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC; - } - - conflict_flag = 0; - if (hwconfig("usb2")) { - conflict_flag++; - cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; - cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2; - } - - if (hwconfig("can3")) { - conflict_flag++; - /* some signals can not enable simultaneous*/ - if (conflict_flag > 1) - goto conflict; - cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; - cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3; - } - - conflict_flag = 0; - if (hwconfig("lcd")) { - conflict_flag++; - cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; - cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD; - } - - if (hwconfig("qe")) { - conflict_flag++; - /* some signals can not enable simultaneous*/ - if (conflict_flag > 1) - goto conflict; - cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; - cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE; - } - - return 0; - -conflict: - printf("WARNING: pin conflict! MUX setting may failed!\n"); - return 0; -} -#endif - -int board_early_init_f(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_TSEC_ENET - /* clear BD & FR bits for BE BD's and frame data */ - clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); -#endif - -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif - - arch_soc_init(); - -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) { - timer_init(); - dram_init(); - } -#endif - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) -{ - void (*second_uboot)(void); - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - - get_clocks(); - -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - preloader_console_init(); - - dram_init(); - - /* Allow OCRAM access permission as R/W */ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - - /* - * if it is woken up from deep sleep, then jump to second - * stage uboot and continue executing without recopying - * it from SD since it has already been reserved in memeory - * in last boot. - */ - if (is_warm_boot()) { - second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE; - second_uboot(); - } - - board_init_r(NULL, 0); -} -#endif - -#ifdef CONFIG_DEEP_SLEEP -/* program the regulator (MC34VR500) to support deep sleep */ -void ls1twr_program_regulator(void) -{ - unsigned int i2c_bus; - u8 i2c_device_id; - -#define LS1TWR_I2C_BUS_MC34VR500 1 -#define MC34VR500_ADDR 0x8 -#define MC34VR500_DEVICEID 0x4 -#define MC34VR500_DEVICEID_MASK 0x0f - - i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); - i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & - MC34VR500_DEVICEID_MASK; - if (i2c_device_id != MC34VR500_DEVICEID) { - printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); - return; - } - - i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); - i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); - i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); - i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); - i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); - - i2c_set_bus_num(i2c_bus); -} -#endif - -int board_init(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - -#ifndef CONFIG_SYS_FSL_NO_SERDES - fsl_serdes_init(); -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - config_serdes_mux(); -#endif -#endif - - ls102xa_smmu_stream_id_init(); - -#ifdef CONFIG_U_QE - u_qe_init(); -#endif - -#ifdef CONFIG_DEEP_SLEEP - ls1twr_program_regulator(); -#endif - return 0; -} - -#if defined(CONFIG_SPL_BUILD) -void spl_board_init(void) -{ - ls102xa_smmu_stream_id_init(); -} -#endif - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_CHAIN_OF_TRUST - fsl_setenv_chain_of_trust(); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ -#ifdef CONFIG_FSL_DEVICE_DISABLE - device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); -#endif -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - config_board_mux(); -#endif - -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif -} -#endif - -#if defined(CONFIG_DEEP_SLEEP) -void board_sleep_prepare(void) -{ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif -} -#endif - -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \ - && !defined(CONFIG_SPL_BUILD) -static void convert_flash_bank(char bank) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - printf("Now switch to boot from flash bank %d.\n", bank); - cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; - cpld_data->vbank = bank; - - printf("Reset board to enable configuration.\n"); - cpld_data->system_rst = CONFIG_RESET; -} - -static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - if (argc != 2) - return CMD_RET_USAGE; - if (strcmp(argv[1], "0") == 0) - convert_flash_bank(BOOT_FROM_UPPER_BANK); - else if (strcmp(argv[1], "1") == 0) - convert_flash_bank(BOOT_FROM_LOWER_BANK); - else - return CMD_RET_USAGE; - - return 0; -} - -U_BOOT_CMD( - boot_bank, 2, 0, flash_bank_cmd, - "Flash bank Selection Control", - "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" -); - -static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - if (argc > 2) - return CMD_RET_USAGE; - if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) - cpld_data->system_rst = CONFIG_RESET; - else if (strcmp(argv[1], "init") == 0) - cpld_data->global_rst = INIT_RESET; - else - return CMD_RET_USAGE; - - return 0; -} - -U_BOOT_CMD( - cpld_reset, 2, 0, cpld_reset_cmd, - "Reset via CPLD", - "conf\n" - " -reset with current CPLD configuration\n" - "init\n" - " -reset and initial CPLD configuration with default value" - -); - -static void print_serdes_mux(void) -{ - char current_serdes; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - current_serdes = cpld_data->serdes_mux; - - printf("Serdes Lane B: "); - if ((current_serdes & MASK_LANE_B) == 0) - printf("SATA,\n"); - else - printf("SGMII 1,\n"); - - printf("Serdes Lane C: "); - if ((current_serdes & MASK_LANE_C) == 0) - printf("SGMII 1,\n"); - else - printf("PCIe,\n"); - - printf("Serdes Lane D: "); - if ((current_serdes & MASK_LANE_D) == 0) - printf("PCIe,\n"); - else - printf("SGMII 2,\n"); - - printf("SGMII 1 is on lane "); - if ((current_serdes & MASK_SGMII) == 0) - printf("C.\n"); - else - printf("B.\n"); -} - -static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - if (argc != 2) - return CMD_RET_USAGE; - if (strcmp(argv[1], "sata") == 0) { - printf("Set serdes lane B to SATA.\n"); - convert_serdes_mux(LANEB_SATA, NEED_RESET); - } else if (strcmp(argv[1], "sgmii1b") == 0) { - printf("Set serdes lane B to SGMII 1.\n"); - convert_serdes_mux(LANEB_SGMII1, NEED_RESET); - } else if (strcmp(argv[1], "sgmii1c") == 0) { - printf("Set serdes lane C to SGMII 1.\n"); - convert_serdes_mux(LANEC_SGMII1, NEED_RESET); - } else if (strcmp(argv[1], "sgmii2") == 0) { - printf("Set serdes lane D to SGMII 2.\n"); - convert_serdes_mux(LANED_SGMII2, NEED_RESET); - } else if (strcmp(argv[1], "pciex1") == 0) { - printf("Set serdes lane C to PCIe X1.\n"); - convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); - } else if (strcmp(argv[1], "pciex2") == 0) { - printf("Set serdes lane C & lane D to PCIe X2.\n"); - convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); - } else if (strcmp(argv[1], "show") == 0) { - print_serdes_mux(); - } else { - return CMD_RET_USAGE; - } - - return 0; -} - -U_BOOT_CMD( - lane_bank, 2, 0, serdes_mux_cmd, - "Multiplexed function setting for SerDes Lanes", - "sata\n" - " -change lane B to sata\n" - "lane_bank sgmii1b\n" - " -change lane B to SGMII1\n" - "lane_bank sgmii1c\n" - " -change lane C to SGMII1\n" - "lane_bank sgmii2\n" - " -change lane D to SGMII2\n" - "lane_bank pciex1\n" - " -change lane C to PCIeX1\n" - "lane_bank pciex2\n" - " -change lane C & lane D to PCIeX2\n" - "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" -); -#endif diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg deleted file mode 100644 index f1a1b63ab77..00000000000 --- a/board/freescale/ls1021atwr/ls102xa_pbi.cfg +++ /dev/null @@ -1,12 +0,0 @@ -#PBI commands - -09570200 ffffffff -09570158 00000300 -8940007c 21f47300 - -#Configure Scratch register -09ee0200 10000000 -#Configure alternate space -09570158 00001000 -#Flush PBL data -096100c0 000FFFFF diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg deleted file mode 100644 index f94997d5384..00000000000 --- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#enable IFC, disable QSPI and DSPI -0608000c 00000000 00000000 00000000 -30000000 00007900 60040a00 21046000 -00000000 00000000 00000000 20000000 -00080000 881b7340 00000000 00000000 diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg deleted file mode 100644 index 541b604cffc..00000000000 --- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#disable IFC, enable QSPI and DSPI -0608000c 00000000 00000000 00000000 -30000000 00007900 60040a00 21046000 -00000000 00000000 00000000 20000000 -20024800 881b7340 00000000 00000000 diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S deleted file mode 100644 index 3c093aa33cb..00000000000 --- a/board/freescale/ls1021atwr/psci.S +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 NXP Semiconductor. - * Author: Wang Dongsheng dongsheng.wang@freescale.com - */ - -#include <config.h> -#include <linux/linkage.h> - -#include <asm/armv7.h> -#include <asm/psci.h> - - .pushsection ._secure.text, "ax" - - .arch_extension sec - - .align 5 - -.globl psci_system_off -psci_system_off: -1: wfi - b 1b - - .popsection diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig deleted file mode 100644 index 97ffa21228e..00000000000 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1021ATWR=y -CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_SECURE_BOOT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_MISC_INIT_R=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" -CONFIG_DM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_FSL_DCU_FB=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_RSA=y -CONFIG_SPL_RSA=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig deleted file mode 100644 index 582f52151fa..00000000000 --- a/configs/ls1021atwr_nor_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1021ATWR=y -CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_MISC_INIT_R=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_DM=y -CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_DM_SCSI=y -CONFIG_SPECIFY_CONSOLE_INDEX=y -CONFIG_DM_SERIAL=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_FSL_DCU_FB=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig deleted file mode 100644 index a567c07062c..00000000000 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1021ATWR=y -CONFIG_SYS_TEXT_BASE=0x60100000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LPUART" -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_MISC_INIT_R=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_FSL_DCU_FB=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig deleted file mode 100644 index 1bcf56aa5d6..00000000000 --- a/configs/ls1021atwr_qspi_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1021ATWR=y -CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" -CONFIG_QSPI_BOOT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_MISC_INIT_R=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_DSPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_FSL_DCU_FB=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig deleted file mode 100644 index 44e59d2acc0..00000000000 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1021ATWR=y -CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SECURE_BOOT=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" -CONFIG_BOOTDELAY=0 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 -CONFIG_SPL_CRYPTO_SUPPORT=y -CONFIG_SPL_HASH_SUPPORT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_BMP=y -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" -CONFIG_DM=y -CONFIG_SPL_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_FSL_DCU_FB=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_RSA=y -CONFIG_SPL_RSA=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig deleted file mode 100644 index 4824a83fb46..00000000000 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1021ATWR=y -CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" -CONFIG_SD_BOOT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_BMP=y -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_FSL_DCU_FB=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig deleted file mode 100644 index 4b01bc42f0e..00000000000 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1021ATWR=y -CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" -CONFIG_SD_BOOT=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0" -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_BMP=y -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_LAYERSCAPE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_DSPI=y -CONFIG_FSL_QSPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_FSL_DCU_FB=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h deleted file mode 100644 index 2c91ae783b5..00000000000 --- a/include/configs/ls1021atwr.h +++ /dev/null @@ -1,505 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARMV7_PSCI_1_0 - -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR - -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_DEEP_SLEEP - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -#define DDR_SDRAM_CFG 0x470c0008 -#define DDR_CS0_BNDS 0x008000bf -#define DDR_CS0_CONFIG 0x80014302 -#define DDR_TIMING_CFG_0 0x50550004 -#define DDR_TIMING_CFG_1 0xbcb38c56 -#define DDR_TIMING_CFG_2 0x0040d120 -#define DDR_TIMING_CFG_3 0x010e1000 -#define DDR_TIMING_CFG_4 0x00000001 -#define DDR_TIMING_CFG_5 0x03401400 -#define DDR_SDRAM_CFG_2 0x00401010 -#define DDR_SDRAM_MODE 0x00061c60 -#define DDR_SDRAM_MODE_2 0x00180000 -#define DDR_SDRAM_INTERVAL 0x18600618 -#define DDR_DDR_WRLVL_CNTL 0x8655f605 -#define DDR_DDR_WRLVL_CNTL_2 0x05060607 -#define DDR_DDR_WRLVL_CNTL_3 0x05050505 -#define DDR_DDR_CDR1 0x80040000 -#define DDR_DDR_CDR2 0x00000001 -#define DDR_SDRAM_CLK_CNTL 0x02000000 -#define DDR_DDR_ZQ_CNTL 0x89080600 -#define DDR_CS0_CONFIG_2 0 -#define DDR_SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG2_D_INIT 0x00000010 -#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 -#define SDRAM_CFG2_FRC_SR 0x80000000 -#define SDRAM_CFG_BI 0x00000001 - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg -#endif - -#ifdef CONFIG_SECURE_BOOT -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. - */ -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_SECURE_BOOT */ - -#define CONFIG_SPL_TEXT_BASE 0x10000000 -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ -#endif - -#define PHYS_SDRAM 0x80000000 -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ - !defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#endif - -/* - * IFC Definitions - */ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_IFC -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TAVDS(0x0) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) | \ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWP(0x1c) | \ - FTIM2_NOR_TWPH(0x0e)) -#define CONFIG_SYS_NOR_FTIM3 0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } - -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_WRITE_SWAPPED_DATA -#endif - -/* CPLD */ - -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) - -/* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ - FTIM0_GPCM_TEADC(0xf) | \ - FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 - -/* - * Serial Port - */ -#ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG -#else -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * MMC - */ - -/* SPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -/* QSPI */ -#define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - -/* DSPI */ -#endif - -/* DM SPI */ -#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) -#define CONFIG_DM_SPI_FLASH -#endif - -/* - * Video - */ -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO - -#define CONFIG_FSL_DCU_SII9022A -#define CONFIG_SYS_I2C_DVI_BUS_NUM 1 -#define CONFIG_SYS_I2C_DVI_ADDR 0x39 -#endif - -/* - * eTSEC - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_PHY_ATHEROS - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_CMDLINE_TAG - -#define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define COUNTER_FREQUENCY 12500000 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 256 - -#define CONFIG_FSL_DEVICE_DISABLE - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) -#include <config_distro_bootcmd.h> - -#ifdef CONFIG_LPUART -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x65000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - BOOTENV \ - "boot_scripts=ls1021atwr_boot.scr\0" \ - "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "installer=load mmc 0:2 $load_addr " \ - "/flex_installer_arm32.itb; " \ - "bootm $load_addr#ls1021atwr\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ - "nor_bootcmd=echo Trying load from nor..;" \ - "cp.b $kernel_addr $load_addr " \ - "$kernel_size && bootm $load_addr#$board\0" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x61000000\0" \ - "kernelheader_addr=0x60800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "kernelheader_size=0x40000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ - BOOTENV \ - "boot_scripts=ls1021atwr_boot.scr\0" \ - "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "nor_bootcmd=echo Trying load from nor..;" \ - "cp.b $kernel_addr $load_addr " \ - "$kernel_size; env exists secureboot " \ - "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo && mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" -#endif - -#undef CONFIG_BOOTCOMMAND -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ - "env exists secureboot && esbc_halt" -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#else -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ - "env exists secureboot && esbc_halt;" -#endif - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_LS102XA_STREAM_ID - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_SYS_QE_FW_ADDR 0x60940000 - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x20000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#include <asm/fsl_secure_boot.h> -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#endif