From: Haiying Wang Haiying.Wang@freescale.com
P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal.
P1021MDS has to load the microcode from NAND flash, this patch defines misc_init_r() for loading ucode and initializing qe.
Signed-off-by: Haiying Wang Haiying.Wang@freescale.com --- v3: make changes in p1021mds.c and P1021MDS.h according to the changes in patch 5/8, update the copyright years.
arch/powerpc/cpu/mpc85xx/speed.c | 4 ++ arch/powerpc/include/asm/immap_85xx.h | 13 +++++ board/freescale/p1021mds/p1021mds.c | 83 +++++++++++++++++++++++++++++++++ drivers/qe/uec.c | 40 +++++++++++++++- include/configs/P1021MDS.h | 47 ++++++++++++++++++ 5 files changed, 186 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f2aa8d0..ae94ee8 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -165,10 +165,14 @@ void get_sys_info (sys_info_t * sysInfo) #endif
#ifdef CONFIG_QE +#ifdef CONFIG_P1021 + sysInfo->freqQE = sysInfo->freqSystemBus; +#else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#endif
#if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 77e3629..9b7de6b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1909,6 +1909,19 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 +#define MPC85xx_PMUXCR_QE0 0x00008000 +#define MPC85xx_PMUXCR_QE1 0x00004000 +#define MPC85xx_PMUXCR_QE2 0x00002000 +#define MPC85xx_PMUXCR_QE3 0x00001000 +#define MPC85xx_PMUXCR_QE4 0x00000800 +#define MPC85xx_PMUXCR_QE5 0x00000400 +#define MPC85xx_PMUXCR_QE6 0x00000200 +#define MPC85xx_PMUXCR_QE7 0x00000100 +#define MPC85xx_PMUXCR_QE8 0x00000080 +#define MPC85xx_PMUXCR_QE9 0x00000040 +#define MPC85xx_PMUXCR_QE10 0x00000020 +#define MPC85xx_PMUXCR_QE11 0x00000010 +#define MPC85xx_PMUXCR_QE12 0x00000008 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ u8 res6[8]; u32 devdisr; /* Device disable control */ diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c index c7a7e57..e1ee1cf 100644 --- a/board/freescale/p1021mds/p1021mds.c +++ b/board/freescale/p1021mds/p1021mds.c @@ -37,6 +37,54 @@ #include <tsec.h> #include <netdev.h>
+#ifdef CONFIG_QE +#ifdef CONFIG_SYS_QE_FW_IN_NAND +#include <nand.h> +#include <asm/errno.h> +#endif +extern void qe_init(uint qe_base); +extern void qe_reset(void); +#endif + +#ifdef CONFIG_QE +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* QE_MUX_MDC */ + {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ + /* QE_MUX_MDIO */ + {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ + + /* UCC_1_MII */ + {0, 23, 2, 0, 2}, /* CLK12 */ + {0, 24, 2, 0, 1}, /* CLK9 */ + {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ + {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ + {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ + {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ + {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ + {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ + {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ + {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ + {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ + {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ + {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ + {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ + {0, 17, 2, 0, 2}, /* ENET1_CRS */ + {0, 16, 2, 0, 2}, /* ENET1_COL */ + + /* UCC_5_RMII */ + {1, 11, 2, 0, 1}, /* CLK13 */ + {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ + {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ + {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ + {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ + {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ + {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ + {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ + + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ +}; +#endif + int board_early_init_f(void) {
@@ -100,6 +148,14 @@ int board_eth_init(bd_t *bis)
tsec_eth_init(bis, tsec_info, num);
+#if defined(CONFIG_UEC_ETH) + /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); + + uec_standard_init(bis); +#endif + return pci_eth_init(bis); } #endif @@ -120,6 +176,10 @@ void ft_board_setup(void *blob, bd_t *bd)
FT_FSL_PCI_SETUP;
+#ifdef CONFIG_QE + do_fixup_by_compat(blob, "fsl,qe", "status", "okay", + sizeof("okay"), 0); +#endif } #endif ; @@ -131,3 +191,26 @@ void board_lmb_reserve(struct lmb *lmb) cpu_mp_lmb_reserve(lmb); } #endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r() +{ +#if defined(CONFIG_QE) && defined(CONFIG_SYS_QE_FW_LENGTH) + int ret; + size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; + + /* load QE firmware from NAND flash to DDR first */ + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + + if (ret && ret == -EUCLEAN) { + printf ("NAND read for QE firmware at offset %x failed %d\n", + CONFIG_SYS_QE_FW_IN_NAND, ret); + } + + qe_init(CONFIG_SYS_IMMR + 0x00080000); + qe_reset(); +#endif + return 0; +} +#endif diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 282ab23..04d7987 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2011 Freescale Semiconductor, Inc. * * Dave Liu daveliu@freescale.com * @@ -30,6 +30,9 @@ #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#ifdef CONFIG_P1021 +#define BCSR11_ENET_MICRST 0x20 +#endif
/* Default UTBIPAR SMI address */ #ifndef CONFIG_UTBIPAR_INIT_TBIPA @@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv;
+#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info);
+#ifdef CONFIG_P1021 + /* + * QE12 is muxed with LBCTL, it needs to be released for enabling + * LBCTL signal for LBC usage. + */ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + /* Adjust the interface according to speed */ adjust_link(dev); } @@ -1198,10 +1217,24 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) { +#ifdef CONFIG_P1021 + /* reset micrel phy for each UEC */ + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST); + udelay(200); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + err = init_phy(dev); if (err) { printf("%s: Cannot initialize PHY, aborting.\n", @@ -1228,6 +1261,11 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (1);
+#ifdef CONFIG_P1021 + /* QE12 needs to be released for enabling LBCTL signal*/ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + if (err || i <= 0) printf("warning: %s: timeout on PHY link\n", dev->name);
diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h index 0496cd3..65226eb 100644 --- a/include/configs/P1021MDS.h +++ b/include/configs/P1021MDS.h @@ -414,6 +414,50 @@ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif /* CONFIG_TSEC_ENET */
+#define CONFIG_QE + +#ifdef CONFIG_QE +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000 +#define CONFIG_SYS_QE_FW_ADDR 0x10000000 +#define CONFIG_SYS_QE_FW_LENGTH 0x10000 + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) + +#define CONFIG_UEC_ETH +#define CONFIG_PHY_MODE_NEED_CHANGE + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define CONFIG_HAS_ETH0 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ +#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH1 */ + +#define CONFIG_UEC_ETH5 /* GETH5 */ +#define CONFIG_HAS_ETH1 + +#ifdef CONFIG_UEC_ETH5 +#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ +#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ +#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ +#define CONFIG_SYS_UEC5_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH2 */ + +#endif /* CONFIG_QE */ + /* * I2C2 EEPROM */ @@ -458,6 +502,8 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #endif
+#define CONFIG_E1000 + #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
@@ -491,6 +537,7 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */
#define CONFIG_MMC #ifdef CONFIG_MMC