This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.
Signed-off-by: York Sun yorksun@freescale.com --- board/freescale/corenet_ds/ddr.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index f8df9d1..07b950f 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -170,8 +170,8 @@ const board_specific_parameters_t board_specific_parameters[][30] = { * lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 0, 850, 4, 1, 5, 0xff, 2, 0}, - {851, 950, 4, 3, 5, 0xff, 2, 0}, + { 0, 850, 4, 4, 6, 0xff, 2, 0}, + {851, 950, 4, 5, 7, 0xff, 2, 0}, {951, 1050, 4, 5, 8, 0xff, 2, 0}, {1051, 1250, 4, 5, 10, 0xff, 2, 0}, {1251, 1350, 4, 5, 11, 0xff, 2, 0}, @@ -188,8 +188,8 @@ const board_specific_parameters_t board_specific_parameters[][30] = { * lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 0, 850, 4, 1, 5, 0xff, 2, 0}, - {851, 950, 4, 3, 5, 0xff, 2, 0}, + { 0, 850, 4, 4, 6, 0xff, 2, 0}, + {851, 950, 4, 5, 7, 0xff, 2, 0}, {951, 1050, 4, 5, 8, 0xff, 2, 0}, {1051, 1250, 4, 5, 10, 0xff, 2, 0}, {1251, 1350, 4, 5, 11, 0xff, 2, 0},