Remove redundant coherency checks before calling cache ops in UDMA driver. This is now handled in arch specific cache operation implementation based on Kconfig option
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com --- drivers/dma/ti/k3-udma.c | 49 +++++++++++++--------------------------- 1 file changed, 16 insertions(+), 33 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 2f82ab0955a4..ee4bc531cb50 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -93,7 +93,6 @@ struct udma_dev { u32 psil_base;
u32 ch_count; - bool is_coherent; };
struct udma_chan { @@ -274,11 +273,6 @@ static inline bool udma_is_chan_running(struct udma_chan *uc) return false; }
-static int udma_is_coherent(struct udma_chan *uc) -{ - return uc->ud->is_coherent; -} - static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr) { struct k3_nav_ring *ring = NULL; @@ -1305,7 +1299,6 @@ static int udma_probe(struct udevice *dev) return ret; }
- ud->is_coherent = dev_read_bool(dev, "dma-coherent"); tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops; tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
@@ -1453,11 +1446,9 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
- if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)tr_desc, - ALIGN((u64)tr_desc + desc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)tr_desc, + ALIGN((u64)tr_desc + desc_size, + ARCH_DMA_MINALIGN));
k3_nav_ringacc_ring_push(uc->tchan->t_ring, &tr_desc);
@@ -1622,14 +1613,12 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type); cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
- if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)dma_src, - ALIGN((u64)dma_src + len, - ARCH_DMA_MINALIGN)); - flush_dcache_range((u64)desc_tx, - ALIGN((u64)desc_tx + uc->hdesc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)dma_src, + ALIGN((u64)dma_src + len, + ARCH_DMA_MINALIGN)); + flush_dcache_range((u64)desc_tx, + ALIGN((u64)desc_tx + uc->hdesc_size, + ARCH_DMA_MINALIGN));
ret = k3_nav_ringacc_ring_push(uc->tchan->t_ring, &uc->desc_tx); if (ret) { @@ -1673,19 +1662,15 @@ static int udma_receive(struct dma *dma, void **dst, void *metadata) }
/* invalidate cache data */ - if (!udma_is_coherent(uc)) { - invalidate_dcache_range((ulong)desc_rx, - (ulong)(desc_rx + uc->hdesc_size)); - } + invalidate_dcache_range((ulong)desc_rx, + (ulong)(desc_rx + uc->hdesc_size));
cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
/* invalidate cache data */ - if (!udma_is_coherent(uc)) { - invalidate_dcache_range((ulong)buf_dma, - (ulong)(buf_dma + buf_dma_len)); - } + invalidate_dcache_range((ulong)buf_dma, + (ulong)(buf_dma + buf_dma_len));
cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
@@ -1790,11 +1775,9 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) cppi5_hdesc_set_pktlen(desc_rx, size); cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
- if (!udma_is_coherent(uc)) { - flush_dcache_range((u64)desc_rx, - ALIGN((u64)desc_rx + uc->hdesc_size, - ARCH_DMA_MINALIGN)); - } + flush_dcache_range((u64)desc_rx, + ALIGN((u64)desc_rx + uc->hdesc_size, + ARCH_DMA_MINALIGN));
k3_nav_ringacc_ring_push(uc->rchan->fd_ring, &desc_rx);