Dear Sergey Yanovich,
Dear Marek Vasut,
On Tue, 2013-05-21 at 21:02 +0200, Marek Vasut wrote:
The whole 256 kB of SRAM could be used for persistent storage with the patch. Without it, part of SRAM should be dedicated for U-Boot stack or be overwritten on boot.
This won't hold on any PXA that uses SPL, like the vpac270 with OneNAND SPL and PXA3xx (which is out of tree, none of your concern ;-) )
I am no way trying to enforce D-Cache as RAM. The patch just provides an option for those who needs it.
I'd love to have a uniform way to do this cache thing, really ...
You are right. After SDRAM is configured, it is enough to turn on data caching to receive its speed benefits.
You must make sure anything that uses DMA won't crash.
I wasn't sure why data cache is disabled in U-Boot for every board I saw configuration of. Thanks for pointing out.
But I don't understand how locking cachelines as RAM and enabling dcache relate to each other in this context.
I meant D-Cache is several times faster than SDRAM, so it may be possible to get a bit faster, if stack remains on D-Cache even after SDRAM is configured.
Not really, enabling dcache altogether and marking DRAM region as cached would be much better.
Repeating my hedge, I don't see the full picture, yet. It may well be impossible (if U-Boot needs more than 32 kB of stack)
No way.
or not worth the effort (if the gain is too small).
The larger gain would be from fixing the U-Boot drivers for PXA to work well with DCache ;-) Then the speedup would really be plenty significant, this can be well confirmed on many other ARM chips.
Best regards, Marek Vasut