Re: [U-Boot] [PATCH 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

On 10/21/2015 03:14 AM, Yuan Yao wrote:

Affects: DDR Description: Memory controller performance is not optimal with default internal target queue register values. Impact: Memory controller performance is not optimal. Workaround: Write a value of 63b2_0002h to address: 157_020Ch.

Please rewrite the commit message to explain why and what this patch does, not copy-n-paste from erratum document.

York