Signed-off-by: Kumar Gala galak@kernel.crashing.org --- Makefile | 1 + board/freescale/mpc8544ds/Makefile | 9 +- board/freescale/mpc8544ds/ddr.c | 268 +++++++++++++++++++++++++++++++++ board/freescale/mpc8544ds/mpc8544ds.c | 21 ++- cpu/mpc85xx/Makefile | 2 +- include/configs/MPC8544DS.h | 59 ++++++-- 6 files changed, 339 insertions(+), 21 deletions(-) create mode 100644 board/freescale/mpc8544ds/ddr.c
diff --git a/Makefile b/Makefile index 39fc369..d0499ba 100644 --- a/Makefile +++ b/Makefile @@ -235,6 +235,7 @@ LIBS += drivers/qe/qe.a endif ifeq ($(CPU),mpc85xx) LIBS += drivers/qe/qe.a +LIBS += cpu/mpc8xxx/libmpc8xxx.a endif ifeq ($(CPU),mpc86xx) LIBS += cpu/mpc8xxx/libmpc8xxx.a diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 53368b2..3e82bbf 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -26,10 +26,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c new file mode 100644 index 0000000..b18ccc7 --- /dev/null +++ b/board/freescale/mpc8544ds/ddr.c @@ -0,0 +1,268 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <../cpu/mpc8xxx/fsl_ddr_sdram.h> + +#define SDRAM_TYPE_DDR1 2 +#define SDRAM_TYPE_DDR2 3 + + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_sdram_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_sdram_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS1); + } +} + + +void +fsl_ddr_sdram_dump_memctl_regs(unsigned int ctrl_num) +{ + unsigned int i; + volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + unsigned int bnds = 0; + unsigned int config = 0; + unsigned int *pbnds = NULL; + unsigned int *pconfig = NULL; + + if (i == 0) { + bnds = ddr->cs0_bnds; + config = ddr->cs0_config; + pbnds = (unsigned int *)&ddr->cs0_bnds; + pconfig = (unsigned int *)&ddr->cs0_config; + + } else if (i == 1) { + bnds = ddr->cs1_bnds; + config = ddr->cs1_config; + pbnds = (unsigned int *)&ddr->cs1_bnds; + pconfig = (unsigned int *)&ddr->cs1_config; + + } else if (i == 2) { + bnds = ddr->cs2_bnds; + config = ddr->cs2_config; + pbnds = (unsigned int *)&ddr->cs2_bnds; + pconfig = (unsigned int *)&ddr->cs2_config; + + } else if (i == 3) { + bnds = ddr->cs3_bnds; + config = ddr->cs3_config; + pbnds = (unsigned int *) &ddr->cs3_bnds; + pconfig = (unsigned int *) &ddr->cs3_config; + + } else { + /* + * FIXME what happens if CONFIG_CHIP_SELECTS_PER_CTRL > 4 + */ + } + + printf("cs%u_bnds = %08X\t%p\n", i, bnds, pbnds); + printf("cs%u_config = %08X\t%p\n", i, config, pconfig); + } + + /* + * Due to inconsistencies between immap_85xx.h and immap_86xx.h, + * you will have to modify the structure member names by hand + * between architectures. + */ + printf("timing_cfg_3 = %08X\t%p\n", + ddr->timing_cfg_3, &ddr->timing_cfg_3); + printf("timing_cfg_0 = %08X\t%p\n", + ddr->timing_cfg_0, &ddr->timing_cfg_0); + printf("timing_cfg_1 = %08X\t%p\n", + ddr->timing_cfg_1, &ddr->timing_cfg_1); + printf("timing_cfg_2 = %08X\t%p\n", + ddr->timing_cfg_2, &ddr->timing_cfg_2); + printf("ddr_sdram_cfg = %08X\t%p\n", + ddr->sdram_cfg, &ddr->sdram_cfg); + printf("ddr_sdram_cfg_2 = %08X\t%p\n", + ddr->sdram_cfg_2, &ddr->sdram_cfg_2); + printf("ddr_sdram_mode = %08X\t%p\n", + ddr->sdram_mode, &ddr->sdram_mode); + printf("ddr_sdram_mode_2 = %08X\t%p\n", + ddr->sdram_mode_2, &ddr->sdram_mode_2); + printf("ddr_sdram_md_cntl = %08X\t%p\n", + ddr->sdram_md_cntl, &ddr->sdram_md_cntl); + printf("ddr_sdram_interval = %08X\t%p\n", + ddr->sdram_interval, &ddr->sdram_interval); + printf("ddr_data_init = %08X\t%p\n", + ddr->sdram_data_init, &ddr->sdram_data_init); + printf("ddr_sdram_clk_cntl = %08X\t%p\n", + ddr->sdram_clk_cntl, &ddr->sdram_clk_cntl); + printf("ddr_init_addr = %08X\t%p\n", + ddr->init_addr, &ddr->init_addr); + printf("ddr_init_ext_addr = %08X\t%p\n", + ddr->init_ext_addr, &ddr->init_ext_addr); +} + + +void +fsl_ddr_sdram_set_memctl_regs(const fsl_memctl_config_regs_t *regs, + unsigned int ctrl_num) +{ + unsigned int i; + volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + ddr->cs0_bnds = regs->cs[i].bnds; + ddr->cs0_config = regs->cs[i].config; + + } else if (i == 1) { + ddr->cs1_bnds = regs->cs[i].bnds; + ddr->cs1_config = regs->cs[i].config; + + } else if (i == 2) { + ddr->cs2_bnds = regs->cs[i].bnds; + ddr->cs2_config = regs->cs[i].config; + + } else if (i == 3) { + ddr->cs3_bnds = regs->cs[i].bnds; + ddr->cs3_config = regs->cs[i].config; + } + } + + /* + * Someone decided to use different names from the documentation... + */ + ddr->timing_cfg_3 = regs->timing_cfg_3; + ddr->timing_cfg_0 = regs->timing_cfg_0; + ddr->timing_cfg_1 = regs->timing_cfg_1; + ddr->timing_cfg_2 = regs->timing_cfg_2; + ddr->sdram_cfg_2 = regs->ddr_sdram_cfg_2; + ddr->sdram_mode = regs->ddr_sdram_mode; + ddr->sdram_mode_2 = regs->ddr_sdram_mode_2; + ddr->sdram_interval = regs->ddr_sdram_interval; + ddr->sdram_data_init = regs->ddr_data_init; + ddr->sdram_clk_cntl = regs->ddr_sdram_clk_cntl; + ddr->init_addr = regs->ddr_init_addr; + ddr->init_ext_addr = regs->ddr_init_ext_addr; + + /* + * FIXME: ECC? Need to program err_disable, err_sbe, and err_int_en + */ + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + asm volatile("sync;isync"); + + ddr->sdram_cfg = regs->ddr_sdram_cfg; + + /* + * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. + */ + while (ddr->sdram_cfg_2 & 0x10) { + udelay(10000); /* throttle polling rate */ + } +} + + +unsigned int +fsl_ddr_sdram_type_function(void) +{ + return SDRAM_TYPE_DDR2; +} + + +/* + * factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * FIXME: need to figure out the function parameters necessary to compute + * FIXME: a clock adjust value + */ + +unsigned int +fsl_ddr_sdram_clk_adjust_function(void) +{ + return 7; +} + + +/* + * factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + * + * FIXME: figure out how to compute or tabulate good values for this + */ + +unsigned int +fsl_ddr_sdram_cpo_override_function(void) +{ + return 10; +} + + +/* + * factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + +unsigned int +fsl_ddr_sdram_write_data_delay_function(void) +{ + return 5; +} + + +/* + * factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + +unsigned int +fsl_ddr_sdram_half_strength_driver_enable_function(void) +{ + return 0; +} diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index dd10af8..d3b2f94 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -24,22 +24,21 @@ #include <command.h> #include <pci.h> #include <asm/processor.h> +#include <asm/mmu.h> #include <asm/immap_85xx.h> #include <asm/immap_fsl_pci.h> #include <asm/io.h> -#include <spd_sdram.h> #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h>
#include "../common/pixis.h" +#include "../cpu/mpc8xxx/fsl_ddr_sdram.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif
-void sdram_init(void); - int board_early_init_f (void) { return 0; @@ -71,7 +70,13 @@ initdram(int board_type)
puts("Initializing\n");
- dram_size = spd_sdram(); + dram_size = fsl_ddr_sdram(); + printf("dram_size = %u\n", dram_size); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + printf("dram_size = %u after setup_ddr_tlbs\n", dram_size); + + dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* @@ -96,10 +101,14 @@ testdram(void) CFG_MEMTEST_END);
printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) + for (p = pstart; p < pend; p++) { + if ((((unsigned int) p) & 0xffff) == 0) { + printf ("%p\n", p); + } *p = 0xaaaaaaaa; + }
- for (p = pstart; p < pend; p++) { + for (p = pstart; p < pend; p++) { if (*p != 0xaaaaaaaa) { printf ("DRAM test fails at: %08x\n", (uint) p); return 1; diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index c180dbd..d51a6dd 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -43,7 +43,7 @@ endif endif
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ - pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \ + pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \ $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index ffe9e00..7878877 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -46,15 +46,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_DLL -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_DDR_ECC_CMD #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/* @@ -87,8 +78,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00400000 +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x7fffffff #define CFG_ALT_MEMTEST #define CONFIG_PANIC_HANG /* do not reset board on panic */
@@ -109,6 +100,49 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#undef CONFIG_DDR_DLL + +//#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +//#define CONFIG_DDR_ECC /* only for ECC DDR module */ +//#define CONFIG_DDR_ECC_CMD + +//#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CFG_DDR_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +/* + * Number of memory controllers on device + */ +#define CONFIG_NUM_DDR_CONTROLLERS 1 + +/* + * Number of DIMM slots per memory controller + */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* + * Number of chip selects per memory controller + * + * The MPC8544 (the chip) has 4 chip selects per memory controller. + * However, the MPC8544DS (the board) has only 1 DIMM slot per memory + * controller, so therefore it only has 2 chip selects per memory + * controller that are actually connected. + */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* + * I2C addresses of SPD EEPROMs + */ +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ + + #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
@@ -260,6 +294,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define CFG_64BIT_STRTOUL 1 +#define CFG_64BIT_VSPRINTF 1 + /* I2C */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */