On Sat, 2013-12-14 at 13:29 +0100, Marek Vasut wrote:
On Saturday, December 14, 2013 at 06:41:57 AM, Sergei Ianovich wrote:
Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS.
If SDRAM is not reset, it causes memory bus congestion and the device hangs.
We put SDRAM in selfresh mode before watchdog reset, removing potential freezes.
Signed-off-by: Sergei Ianovich ynvich@gmail.com
arch/arm/cpu/pxa/pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index c9a7d45..93ca2f0 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -281,5 +281,5 @@ void reset_cpu(ulong ignored) writel(tmp, OSMR3);
for (;;)
;
writel(MDREFR_SLFRSH, MDREFR);Do you need to write this register in an endless loop ?
I didn't think this way. We need to have at least 3, but up to 5 cycles to put SDRAM in SLFRFRSH. It depends on the current state of SDRAM. There is no way to know.
It can probably work if we write just once. But if we have another thread doing something with SDRAM in between, we will still hang. I am not sure how likely is the situation, though.