u-boot makes a fixup for LS1046AQDS board to setup the properties 'fixed-link' and 'phy-connection-type' to 'xgmii' but in case of backplane mode this fixup is not correct because it causes the KR link to fail and so it must be bypassed in order to keep the link in KR mode as it is defined in DTS.
Signed-off-by: Florinel Iordache florinel.iordache@nxp.com --- board/freescale/ls1046aqds/eth.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index d3e8831..1fd755c 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */
#include <common.h> @@ -153,6 +154,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { struct fixed_link f_link; + u32 *handle; + char *prop = NULL; + int off;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { switch (port) { @@ -208,16 +212,27 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "qsgmii"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && (port == FM1_10GEC1 || port == FM1_10GEC2)) { - /* XFI interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for XFI */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); + handle = fdt_getprop(fdt, offset, "phy-handle", NULL); + prop = NULL; + if (handle) { + off = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(*handle)); + prop = fdt_getprop(fdt, off, "backplane-mode", NULL); + } + if (!prop || strcmp(prop, "10gbase-kr")) { + /* XFI interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(10000); + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "xgmii"); + } } }