This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF, which are clock gates in the HDMI output path for the RK3399.
As these are enabled by default (i.e. after reset), we don't implement any logic to actively open/close these clock gates and simply assume that their reset-default has not been changed.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
Changes in v2: None
drivers/clk/rockchip/clk_rk3399.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 72395e2..d820ea6 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -879,6 +879,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART0: case SCLK_UART2: return 24000000; + break; + case PCLK_HDMI_CTRL: + break; case DCLK_VOP0: case DCLK_VOP1: break; @@ -916,6 +919,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI0...SCLK_SPI5: ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); break; + case PCLK_HDMI_CTRL: + case PCLK_VIO_GRF: + /* the PCLK gates for video are enabled by default */ + break; case DCLK_VOP0: case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);