Signed-off-by: Michael Schwingen michael@schwingen.org
diff --git a/include/configs/actux3.h b/include/configs/actux3.h new file mode 100644 index 0000000..9492f95 --- /dev/null +++ b/include/configs/actux3.h @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael@schwingen.org + * + * Configuration settings for the AcTux-3 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ +#define CONFIG_ACTUX3 1 /* on an AcTux-3 Board */ + +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ +#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ + +#define CFG_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + + + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTCOMMAND "run boot_flash" +//#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + + + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00010000 /* default load address */ + +#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Expansion bus settings + */ +#define CFG_EXP_CS0 0xbd113442 + +/* + * SDRAM settings + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define CFG_DRAM_BASE 0x00000000 + + +// 16MB SDRAM +# define CFG_SDR_CONFIG 0x3A +# define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x01000000 + + +/* + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 140 /* max number of sectors on one chip */ +#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/* + * environment organization + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 /* size of one complete sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CFG_USE_PPCENV 1 + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ + "kerneladdr=50050000\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000; loady ${loadaddr}; run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000; tftp ${loadaddr} u-boot.bin; run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff; protect off 50006000 5003ffff; erase 50000000 50003fff; erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000; cp.b 16000 50006000 3a000\0" \ + "eraseenv=protect off 50004000 50005fff; erase 50004000 50005fff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};era ${rootaddr} +${filesize}; cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};era ${kerneladdr} +${filesize}; cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3 rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3 rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth; bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth; tftpboot ${loadaddr} ${kernelfile}; bootm\0" \ + + +/* + * Ethernet + */ +#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 /* use separate flash sector with ucode images */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0x10 /* NPE0 PHY address */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MII_ETHSWITCH 1 /* ethernet switch connected to MII port */ + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS /* NFS support */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c new file mode 100644 index 0000000..bc3a128 --- /dev/null +++ b/board/actux3/actux3.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael@schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> + +#include <miiphy.h> + +#include "actux3_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ +int board_post_init (void) +{ + return (0); +} + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX3; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_ENABLE(CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CFG_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE(CFG_GPIO_DSR); + GPIO_OUTPUT_ENABLE(CFG_GPIO_DCD); + GPIO_OUTPUT_ENABLE(CFG_GPIO_LED5_GN); + GPIO_OUTPUT_ENABLE(CFG_GPIO_LED6_RT); + GPIO_OUTPUT_ENABLE(CFG_GPIO_LED6_GN); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR); + GPIO_OUTPUT_SET (CFG_GPIO_DCD); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN); + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT); + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN); + + /* + * Setup GPIO's for Interrupt inputs + */ + GPIO_OUTPUT_DISABLE(CFG_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE(CFG_GPIO_ETHINT); + + /* + * Setup GPIO's for 33MHz clock output + */ + GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK); + *IXP425_GPIO_GPCLKR = 0x011001FF; + + *IXP425_EXP_CS1 = 0x94d10013; // CS1: IPAC-X + *IXP425_EXP_CS5 = 0x9d520003; // CS5: Debug port + *IXP425_EXP_CS6 = 0x81860001; // CS6: HwRel + *IXP425_EXP_CS7 = 0x80900003; // CS7: LED + + udelay (533); + GPIO_OUTPUT_SET(CFG_GPIO_IORST); + GPIO_OUTPUT_SET(CFG_GPIO_ETHRST); + + ACTUX3_LED1_RT(1); + ACTUX3_LED1_GN(0); + ACTUX3_LED2_RT(0); + ACTUX3_LED2_GN(0); + ACTUX3_LED3_RT(0); + ACTUX3_LED3_GN(0); + ACTUX3_LED4_GN(0); + ACTUX3_LED5_RT(0); + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard(void) +{ + char revision; + char *s = getenv("serial#"); + + puts("Board: AcTux-3 rev."); + putc(ACTUX3_BOARDREL + 'A' - 1); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = reserved + * 1 = Rev. A + * 2 = Rev. B + *************************************************************************/ +u32 get_board_rev(void) +{ + return ACTUX3_BOARDREL; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +void reset_phy(void) +{ + int i; + + /* initialize the PHY */ + miiphy_reset("NPE0", CONFIG_PHY_ADDR); + + /* all LED outputs = Link/Act */ + miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); + + /* set all ethernet switch ports to forwarding state */ + for (i=1; i <=5; i++) + miiphy_write("NPE0", CONFIG_PHY_ADDR+8+i, 0x04, 0x03); + +} diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h new file mode 100644 index 0000000..00e0bad --- /dev/null +++ b/board/actux3/actux3_hw.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael@schwingen.org + * + * hardware register definitions for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX3_HW_H +#define _ACTUX3_HW_H + +// 0 = LED off,1 = ON +#define ACTUX3_LED1_RT(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 0)) = (a) +#define ACTUX3_LED1_GN(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 1)) = (a) +#define ACTUX3_LED2_RT(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 2)) = (a) +#define ACTUX3_LED2_GN(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 3)) = (a) +#define ACTUX3_LED3_RT(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 4)) = (a) +#define ACTUX3_LED3_GN(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 5)) = (a) +#define ACTUX3_LED4_GN(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 6)) = ((a)^1) +#define ACTUX3_LED5_RT(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 7)) = (a) + +#define ACTUX3_DBG_PORT ((volatile u8 *)(IXP425_EXP_BUS_CS5_BASE_PHYS)) +#define ACTUX3_BOARDREL ((*(volatile u8 *)IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) +#define ACTUX3_OPTION ((*(volatile u8 *)IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) + + +/* + * GPIO settings + */ +#define CFG_GPIO_DBGINT 0 +#define CFG_GPIO_ETHINT 1 +#define CFG_GPIO_ETHRST 2 // Out +#define CFG_GPIO_LED5_GN 3 // Out +#define CFG_GPIO_LED6_RT 4 // Out +#define CFG_GPIO_LED6_GN 5 // Out +#define CFG_GPIO_DSR 6 // Out +#define CFG_GPIO_DCD 7 // Out +#define CFG_GPIO_DBGJUMPER 9 +#define CFG_GPIO_BUTTON1 10 +#define CFG_GPIO_DBGSENSE 11 +#define CFG_GPIO_DTR 12 +#define CFG_GPIO_IORST 13 // Out +#define CFG_GPIO_PCI_CLK 14 // Out +#define CFG_GPIO_EXTBUS_CLK 15 // Out + + + + +#endif + diff --git a/board/actux3/config.mk b/board/actux3/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux3/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds new file mode 100644 index 0000000..25eb7bf --- /dev/null +++ b/board/actux3/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/ixp/start.o (.text) + /* WARNING - the following is hand-optimized to fit within + the sector before the environment sector. If it throws an + error during compilation remove an object here to get it + linked after the configuration sector. */ + lib_generic/string.o (.text) + lib_generic/vsprintf.o (.text) + lib_arm/board.o (.text) + common/dlmalloc.o (.text) + drivers/mtd/cfi_flash.o (.text) + cpu/ixp/cpu.o (.text) + + . = env_offset; + common/environment.o (.ppcenv) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +}