[U-Boot] [PATCH v2] board: atmel: add SAMA5D2 ICP board

From: Eugen Hristev eugen.hristev@microchip.com

The SAMA5D2 ICP Board features the SAMA5D27 SoC, together with QSPI Flash, Wilc3000 wireless device and EtherCat support.

Signed-off-by: Eugen Hristev eugen.hristev@microchip.com ---

Changes in v2: - created at91-sama5d2_icp-u-boot.dtsi with the pre-reloc properties - removed some #ifdef as suggested by Stefan - fixed issue with wrong SPL FAT FS in defconfig - fixed build issue with wrong DRAM_BANKS redefine

arch/arm/dts/Makefile | 3 + arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi | 30 +++++ arch/arm/dts/at91-sama5d2_icp.dts | 95 +++++++++++++++ arch/arm/mach-at91/Kconfig | 12 ++ board/atmel/sama5d2_icp/Kconfig | 15 +++ board/atmel/sama5d2_icp/MAINTAINERS | 7 ++ board/atmel/sama5d2_icp/Makefile | 7 ++ board/atmel/sama5d2_icp/sama5d2_icp.c | 191 ++++++++++++++++++++++++++++++ configs/sama5d2_icp_mmc_defconfig | 73 ++++++++++++ include/configs/sama5d2_icp.h | 69 +++++++++++ 10 files changed, 502 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi create mode 100644 arch/arm/dts/at91-sama5d2_icp.dts create mode 100644 board/atmel/sama5d2_icp/Kconfig create mode 100644 board/atmel/sama5d2_icp/MAINTAINERS create mode 100644 board/atmel/sama5d2_icp/Makefile create mode 100644 board/atmel/sama5d2_icp/sama5d2_icp.c create mode 100644 configs/sama5d2_icp_mmc_defconfig create mode 100644 include/configs/sama5d2_icp.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 930b7e0..a3bfb11 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -643,6 +643,9 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ at91-sama5d27_som1_ek.dtb

+dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \ + at91-sama5d2_icp.dtb + dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ sama5d31ek.dtb \ sama5d33ek.dtb \ diff --git a/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi new file mode 100644 index 0000000..347fa81 --- /dev/null +++ b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama5d2_icp-for-uboot.dtsi - Device Tree file for SAMA5D2 ICP board + * SAMA5D2 Industrial Connectivity Platform + * + * Copyright (c) 2019, Microchip Technology Inc. and its subsidiaries + * 2019, Eugen Hristev eugen.hristev@microchip.com + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + }; +}; + +&sdmmc0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { /* mikrobus1 uart */ + u-boot,dm-pre-reloc; +}; + +&pinctrl_sdmmc0_default { + u-boot,dm-pre-reloc; +}; + +&pinctrl_mikrobus1_uart { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts new file mode 100644 index 0000000..e777754 --- /dev/null +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board + * SAMA5D2 Industrial Connectivity Board + * + * Copyright (c) 2018, Microchip Technology Inc. + * 2018, Eugen Hristev eugen.hristev@microchip.com + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" + +/ { + model = "Microchip SAMA5D2 ICP"; + compatible = "atmel,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; + i2c1 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ahb { + + sdmmc0: sdio-host@a0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; + }; + + apb { + uart0: serial@f801c000 { /* mikrobus1 uart */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + status = "okay"; + }; + + i2c1: i2c@fc028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c32"; + reg = <0x53>; + pagesize = <16>; + }; + }; + pioA: gpio@fc038000 { + status = "okay"; + pinctrl { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD19__TWD1>, + <PIN_PD20__TWCK1>; + bias-disable; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA0__SDMMC0_CK>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a089e94..c3b21b7 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -180,6 +180,17 @@ config TARGET_SAMA5D27_SOM1_EK processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM in a single package.

+config TARGET_SAMA5D2_ICP + bool "SAMA5D2 Industrial Connectivity Platform (ICP)" + select CPU_V7A + select SUPPORT_SPL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + help + The SAMA5D2 ICP embeds SAMA5D27 rev. C SoC, together with + a 64Mbit QSPI flash, 3xMikrobus connectors, 4xUSB , + EtherCat and WILC3000 devices on board. + config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" select BOARD_EARLY_INIT_F @@ -281,6 +292,7 @@ source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" +source "board/atmel/sama5d2_icp/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" diff --git a/board/atmel/sama5d2_icp/Kconfig b/board/atmel/sama5d2_icp/Kconfig new file mode 100644 index 0000000..3859845 --- /dev/null +++ b/board/atmel/sama5d2_icp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_ICP + +config SYS_BOARD + default "sama5d2_icp" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_icp" + +endif diff --git a/board/atmel/sama5d2_icp/MAINTAINERS b/board/atmel/sama5d2_icp/MAINTAINERS new file mode 100644 index 0000000..db984b6 --- /dev/null +++ b/board/atmel/sama5d2_icp/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 ICP BOARD +M: Eugen Hristev eugen.hristev@microchip.com +S: Maintained +F: board/atmel/sama5d2_icp/ +F: include/configs/sama5d2_icp.h +F: configs/sama5d2_icp_mmc_defconfig + diff --git a/board/atmel/sama5d2_icp/Makefile b/board/atmel/sama5d2_icp/Makefile new file mode 100644 index 0000000..fd7e870 --- /dev/null +++ b/board/atmel/sama5d2_icp/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Microchip Technology Inc. +# Eugen Hristev eugen.hristev@microchip.com +# + +obj-y += sama5d2_icp.o diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c new file mode 100644 index 0000000..807cfcd --- /dev/null +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Microchip Technology, Inc. + * Eugen Hristev eugen.hristev@microchip.com + */ + +#include <common.h> +#include <debug_uart.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_late_init(void) +{ + return 0; +} + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(ATMEL_ID_UART0); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#define MAC24AA_MAC_OFFSET 0xfa + +int misc_init_r(void) +{ +#ifdef CONFIG_I2C_EEPROM + at91_set_ethaddr(MAC24AA_MAC_OFFSET); +#endif + return 0; +} + +/* SPL */ +#ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_SD_BOOT +void spl_mmc_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); +} +#endif + +void spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT + spl_mmc_init(); +#endif +} + +void spl_display_print(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x298; + + ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x5355, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(82) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig new file mode 100644 index 0000000..49b6f54 --- /dev/null +++ b/configs/sama5d2_icp_mmc_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x26f00000 +CONFIG_TARGET_SAMA5D2_ICP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf801c000 +CONFIG_DEBUG_UART_CLOCK=83000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DISPLAY_PRINT=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_icp" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h new file mode 100644 index 0000000..afcd22b --- /dev/null +++ b/include/configs/sama5d2_icp.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D2 ICP Board. + * + * Copyright (C) 2018 Microchip Corporation + * Eugen Hristev eugen.hristev@microchip.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_MISC_INIT_R + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +/* SPI flash */ +#define CONFIG_SF_DEFAULT_SPEED 66000000 + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_SD_BOOT +/* u-boot env in sd/mmc card */ +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +#endif + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#endif + +#endif