+Heinrich Schuchardt for review too
Hi Zhiqiang,
On Fri, 26 Jul 2024 at 11:30, Zhiqiang Hou Zhiqiang.Hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus as a example.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V3:
- New patch.
doc/usage/cmd/cpu.rst | 82 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 doc/usage/cmd/cpu.rst
I think you have left behind the review tags I sent on the previous version. You should pick those up for the next version ('patman status' can do it for you).
diff --git a/doc/usage/cmd/cpu.rst b/doc/usage/cmd/cpu.rst new file mode 100644 index 00000000000..0970e57d5b5 --- /dev/null +++ b/doc/usage/cmd/cpu.rst @@ -0,0 +1,82 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2024 NXP
+.. index::
- single: cpu (command)
+cpu command +===========
+Synopsis +--------
+::
- cpu list
- cpu detail
- cpu release <core ID> <addr>
+Description +-----------
+The *cpu* command prints information about the CPUs, and release a CPU core +to a given address to run applications.
+Example +-------
We normally put the examples at the bottom, after all subcommands have been explained.
+cpu list +~~~~~~~~ +List and print brief information of all the CPU cores On i.MX8M Plus EVK: +::
- u-boot=> cpu list
0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C
Are there blank lines here? It seems like there should not be?
1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30C2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31C+cpu detail +~~~~~~~~~~ +Print more details of all the CPU cores On i.MX8M Plus EVK: +::
- u-boot=> cpu detail
0: cpu@0 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31CID = 0, freq = 1.2 GHz: L1 cache, MMU1: cpu@1 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 30CID = 0, freq = 1.2 GHz: L1 cache, MMU2: cpu@2 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31CID = 0, freq = 1.2 GHz: L1 cache, MMU3: cpu@3 NXP i.MX8MP Rev1.1 A53 at 1200 MHz at 31CID = 0, freq = 1.2 GHz: L1 cache, MMU+cpu release +~~~~~~~~~~~ +On i.MX8M Plus EVK, release the LAST core to run a RTOS application, +the <core ID> is the sequence number refer to the 'cpu list': +::
u-boot=> load mmc 1:2 C0000000 /hello_world.bin66008 bytes read in 5 ms (12.6 MiB/s)u-boot=> dcache flush; icache flushu-boot=> cpu release 3 C0000000
lower-case c
Released CPU core (mpidr: 0x3) to address 0xc0000000+Configuration +-------------
+The cpu command is available if CONFIG_CMD_CPU=y.
+Return code +-----------
+The return value $? is set to 0 (true) if the command is successful,
+1 (false) otherwise.
2.43.0
Regards, Simon