Add basic PCI endpoint sandbox testing.
Signed-off-by: Ramon Fried ramon.fried@gmail.com ---
Changes in v3: - Added more testing of sandbox driver
arch/sandbox/include/asm/test.h | 8 +++++ test/dm/Makefile | 1 + test/dm/pci_ep.c | 64 +++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) create mode 100644 test/dm/pci_ep.c
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index fc52f47f82..cfb30cb376 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -185,4 +185,12 @@ int sandbox_get_beep_frequency(struct udevice *dev); */ int sandbox_get_pch_spi_protect(struct udevice *dev);
+/** + * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count + * + * @dev: Device to check + * @return irq count + */ +int sandbox_get_pci_ep_irq_count(struct udevice *dev); + #endif diff --git a/test/dm/Makefile b/test/dm/Makefile index 49857c5092..fe36f8df47 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -30,6 +30,7 @@ obj-y += ofnode.o obj-$(CONFIG_OSD) += osd.o obj-$(CONFIG_DM_VIDEO) += panel.o obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o obj-$(CONFIG_PCH) += pch.o obj-$(CONFIG_PHY) += phy.o obj-$(CONFIG_POWER_DOMAIN) += power-domain.o diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c new file mode 100644 index 0000000000..101f861751 --- /dev/null +++ b/test/dm/pci_ep.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Ramon Fried + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/test.h> +#include <dm/test.h> +#include <test/ut.h> +#include <hexdump.h> +#include <pci_ep.h> + +/* Test that sandbox PCI EP works correctly */ +static int dm_test_pci_ep_base(struct unit_test_state *uts) +{ + struct udevice *bus; + struct pci_bar tmp_bar; + struct pci_ep_header tmp_header; + int i; + + struct pci_ep_header ep_header = { + .vendorid = 0x1234, + .deviceid = 0x2020, + .revid = 1, + .interrupt_pin = PCI_INTERRUPT_INTA, + }; + + struct pci_bar bar = { + .phys_addr = 0x80000000, + .size = 0x100000, + .barno = BAR_0, + .flags = PCI_BASE_ADDRESS_MEM_TYPE_64 | + PCI_BASE_ADDRESS_MEM_PREFETCH, + }; + + ut_assertok(uclass_get_device(UCLASS_PCI_EP, 0, &bus)); + ut_assertnonnull(bus); + + ut_assertok(pci_ep_write_header(bus, 0, &ep_header)); + ut_assertok(pci_ep_read_header(bus, 0, &tmp_header)); + ut_asserteq_mem(&tmp_header, &ep_header, sizeof(ep_header)); + + ut_assertok(pci_ep_set_msi(bus, 0, 4)); + ut_asserteq(pci_ep_get_msi(bus, 0), 4); + + ut_assertok(pci_ep_set_msix(bus, 0, 360)); + ut_asserteq(pci_ep_get_msix(bus, 0), 360); + + ut_assertok(pci_ep_set_bar(bus, 0, &bar)); + + ut_assertok(pci_ep_read_bar(bus, 0, &tmp_bar, BAR_0)); + ut_asserteq_mem(&tmp_bar, &bar, sizeof(bar)); + + for (i = 0; i < 10; i++) + ut_assertok(pci_ep_raise_irq(bus, 0, 1, PCI_EP_IRQ_LEGACY)); + + ut_asserteq(sandbox_get_pci_ep_irq_count(bus), 10); + return 0; +} + +DM_TEST(dm_test_pci_ep_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); +