Re: [U-Boot] [U-Boot,2/7] rockchip: rk322x: add clock driver

On Fri, 9 Jun 2017, Kever Yang wrote:

Add clock driver init support for:

• cpu, bus clock init;
• emmc, sdmmc clock;
• ddr clock;

Signed-off-by: Kever Yang kever.yang@rock-chips.com

arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 ++++++++++++ drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk322x.c | 413 ++++++++++++++++++++++++ 3 files changed, 629 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h create mode 100644 drivers/clk/rockchip/clk_rk322x.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h new file mode 100644 index 0000000..0a01f87 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -0,0 +1,215 @@ +/*

• • (C) Copyright 2015 Rockchip Electronics Co., Ltd
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef _ASM_ARCH_CRU_RK322X_H +#define _ASM_ARCH_CRU_RK322X_H

+#include <common.h>

+#define MHz 1000000 +#define OSC_HZ (24 * MHz)

+#define APLL_HZ (600 * MHz) +#define GPLL_HZ (594 * MHz)

+#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000

+#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000

+#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000

+/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk322x_clk_priv {

• struct rk322x_cru *cru;
• ulong rate;

+};

+struct rk322x_cru {

• struct rk322x_pll {

• unsigned int con0;
  

• unsigned int con1;
  

• unsigned int con2;
  

• } pll[4];
• unsigned int reserved0[4];
• unsigned int cru_mode_con;
• unsigned int cru_clksel_con[35];
• unsigned int cru_clkgate_con[16];
• unsigned int cru_softrst_con[9];
• unsigned int cru_misc_con;
• unsigned int reserved1[2];
• unsigned int cru_glb_cnt_th;
• unsigned int reserved2[3];
• unsigned int cru_glb_rst_st;
• unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];

It took me a moment to understand why the 'minus one'.

Could you introduce a macro for this along the lines of U32_ELEMS_START_TO_LAST(0x1c0, 0x14c) or something similar... I fail to come up with a concise name that clearly says "from 0x1c0 and covering up to, but excluding, the address 0x150").

• unsigned int cru_sdmmc_con[2];
• unsigned int cru_sdio_con[2];
• unsigned int reserved4[2];
• unsigned int cru_emmc_con[2];
• unsigned int reserved5[4];
• unsigned int cru_glb_srst_fst_value;
• unsigned int cru_glb_srst_snd_value;
• unsigned int cru_pll_mask_con;

+}; +check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);

+struct pll_div {

• u32 refdiv;
• u32 fbdiv;
• u32 postdiv1;
• u32 postdiv2;
• u32 frac;

+};

+enum {

• /* PLLCON0*/
• PLL_BP_SHIFT = 15,
• PLL_POSTDIV1_SHIFT = 12,
• PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
• PLL_FBDIV_SHIFT = 0,
• PLL_FBDIV_MASK = 0xfff,
• /* PLLCON1 */
• PLL_RST_SHIFT = 14,
• PLL_PD_SHIFT = 13,
• PLL_PD_MASK = 1 << PLL_PD_SHIFT,
• PLL_DSMPD_SHIFT = 12,
• PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
• PLL_LOCK_STATUS_SHIFT = 10,
• PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
• PLL_POSTDIV2_SHIFT = 6,
• PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
• PLL_REFDIV_SHIFT = 0,
• PLL_REFDIV_MASK = 0x3f,
• /* CRU_MODE */
• GPLL_MODE_SHIFT = 12,
• GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT,
• GPLL_MODE_SLOW = 0,
• GPLL_MODE_NORM,
• CPLL_MODE_SHIFT = 8,
• CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
• CPLL_MODE_SLOW = 0,
• CPLL_MODE_NORM,
• DPLL_MODE_SHIFT = 4,
• DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
• DPLL_MODE_SLOW = 0,
• DPLL_MODE_NORM,
• APLL_MODE_SHIFT = 0,
• APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
• APLL_MODE_SLOW = 0,
• APLL_MODE_NORM,
• /* CRU_CLK_SEL0_CON */
• BUS_ACLK_PLL_SEL_SHIFT = 13,
• BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
• BUS_ACLK_PLL_SEL_APLL = 0,
• BUS_ACLK_PLL_SEL_GPLL,
• BUS_ACLK_PLL_SEL_HDMIPLL,
• BUS_ACLK_DIV_SHIFT = 8,
• BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
• CORE_CLK_PLL_SEL_SHIFT = 6,
• CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT,
• CORE_CLK_PLL_SEL_APLL = 0,
• CORE_CLK_PLL_SEL_GPLL,
• CORE_CLK_PLL_SEL_DPLL,
• CORE_DIV_CON_SHIFT = 0,
• CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
• /* CRU_CLK_SEL1_CON */
• BUS_PCLK_DIV_SHIFT = 12,
• BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
• BUS_HCLK_DIV_SHIFT = 8,
• BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
• CORE_ACLK_DIV_SHIFT = 4,
• CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
• CORE_PERI_DIV_SHIFT = 0,
• CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
• /* CRU_CLKSEL5_CON */
• GMAC_OUT_PLL_SHIFT = 15,
• GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT,
• GMAC_OUT_DIV_SHIFT = 8,
• GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT,
• MAC_PLL_SEL_SHIFT = 7,
• MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
• RMII_EXTCLK_SLE_SHIFT = 5,
• RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT,
• RMII_EXTCLK_SEL_INT = 0,
• RMII_EXTCLK_SEL_EXT,
• CLK_MAC_DIV_SHIFT = 0,
• CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT,
• /* CRU_CLKSEL10_CON */
• PERI_PCLK_DIV_SHIFT = 12,
• PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT,
• PERI_PLL_SEL_SHIFT = 10,
• PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
• PERI_PLL_CPLL = 0,
• PERI_PLL_GPLL,
• PERI_PLL_HDMIPLL,
• PERI_HCLK_DIV_SHIFT = 8,
• PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
• PERI_ACLK_DIV_SHIFT = 0,
• PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
• /* CRU_CLKSEL11_CON */
• EMMC_PLL_SHIFT = 12,
• EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
• EMMC_SEL_APLL = 0,
• EMMC_SEL_DPLL,
• EMMC_SEL_GPLL,
• EMMC_SEL_24M,
• SDIO_PLL_SHIFT = 10,
• SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
• SDIO_SEL_APLL = 0,
• SDIO_SEL_DPLL,
• SDIO_SEL_GPLL,
• SDIO_SEL_24M,
• MMC0_PLL_SHIFT = 8,
• MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
• MMC0_SEL_APLL = 0,
• MMC0_SEL_DPLL,
• MMC0_SEL_GPLL,
• MMC0_SEL_24M,
• MMC0_DIV_SHIFT = 0,
• MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT,
• /* CRU_CLKSEL12_CON */
• EMMC_DIV_SHIFT = 8,
• EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
• SDIO_DIV_SHIFT = 0,
• SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT,
• /* CRU_CLKSEL26_CON */
• DDR_CLK_PLL_SEL_SHIFT = 8,
• DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT,
• DDR_CLK_SEL_DPLL = 0,
• DDR_CLK_SEL_GPLL,
• DDR_CLK_SEL_APLL,
• DDR_DIV_SEL_SHIFT = 0,
• DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT,
• /* CRU_CLKSEL27_CON */
• VOP_DCLK_DIV_SHIFT = 8,
• VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT,
• VOP_PLL_SEL_SHIFT = 1,
• VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT,
• /* CRU_CLKSEL29_CON */
• GMAC_CLK_SRC_SHIFT = 12,
• GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT,
• /* CRU_SOFTRST5_CON */
• DDRCTRL_PSRST_SHIFT = 11,
• DDRCTRL_SRST_SHIFT = 10,
• DDRPHY_PSRST_SHIFT = 9,
• DDRPHY_SRST_SHIFT = 8,

+}; +#endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e404c0c..c50aff2 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -6,6 +6,7 @@

obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o +obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c new file mode 100644 index 0000000..582ef88 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -0,0 +1,413 @@ +/*

• • (C) Copyright 2015 Google, Inc
• • SPDX-License-Identifier: GPL-2.0
• */

+#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk322x.h> +#include <asm/arch/hardware.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include <linux/log2.h>

+DECLARE_GLOBAL_DATA_PTR;

+enum {

• VCO_MAX_HZ = 3200U * 1000000,
• VCO_MIN_HZ = 800 * 1000000,
• OUTPUT_MAX_HZ = 3200U * 1000000,
• OUTPUT_MIN_HZ = 24 * 1000000,

+};

+#define RATE_TO_DIV(input_rate, output_rate) \

• ((input_rate) / (output_rate) - 1);

The RATE_TO_DIV macro remains unused below.

+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))

+#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\

• .refdiv = _refdiv,\
• .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
• .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
• _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \

• 	 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
  

• 	 #hz "Hz cannot be hit with PLL "\
  

• 	 "divisors on line " __stringify(__LINE__));
  

+/* use interge mode*/

typo: integer

+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);

+static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,

• 	 const struct pll_div *div)
  

+{

• int pll_id = rk_pll_id(clk_id);
• struct rk322x_pll *pll = &cru->pll[pll_id];
• /* All PLLs have same VCO and output frequency range restrictions. */
• uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
• uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
• debug("PLL at %x: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",

•      pll, div->fbdiv, div->refdiv, div->postdiv1,
  

•      div->postdiv2, vco_hz, output_hz);
  

• assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&

•       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  

• /* use interger mode */
• rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
• /* Power down */
• rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
• rk_clrsetreg(&pll->con0,

•      PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  

•      (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  

• rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,

•      (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  

•      div->refdiv << PLL_REFDIV_SHIFT));
  

• /* Power Up */
• rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
• /* waiting for pll lock */
• while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))

• udelay(1);
  

• return 0;

+}

+static void rkclk_init(struct rk322x_cru *cru) +{

• u32 aclk_div;
• u32 hclk_div;
• u32 pclk_div;
• /* pll enter slow-mode */
• rk_clrsetreg(&cru->cru_mode_con,

•      GPLL_MODE_MASK | APLL_MODE_MASK,
  

•      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  

•      APLL_MODE_SLOW << APLL_MODE_SHIFT);
  

• /* init pll */
• rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
• rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
• /*

• * select apll as cpu/core clock pll source and
  

• * set up dependent divisors for PERI and ACLK clocks.
  

• * core hz : apll = 1:1
  

• */
  

• aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
• assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
• pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
• assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
• rk_clrsetreg(&cru->cru_clksel_con[0],

•      CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
  

•      CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  

•      0 << CORE_DIV_CON_SHIFT);
  

• rk_clrsetreg(&cru->cru_clksel_con[1],

•      CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
  

•      aclk_div << CORE_ACLK_DIV_SHIFT |
  

•      pclk_div << CORE_PERI_DIV_SHIFT);
  

• /*

• * select apll as pd_bus bus clock source and
  

• * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  

• */
  

• aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
• assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
• pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
• assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
• hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
• assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
• rk_clrsetreg(&cru->cru_clksel_con[0],

•      BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  

•      BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
  

•      aclk_div << BUS_ACLK_DIV_SHIFT);
  

• rk_clrsetreg(&cru->cru_clksel_con[1],

•      BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
  

•      pclk_div << BUS_PCLK_DIV_SHIFT |
  

•      hclk_div << BUS_HCLK_DIV_SHIFT);
  

• /*

• * select gpll as pd_peri bus clock source and
  

• * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  

• */
  

• aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
• assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
• hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
• assert((1 << hclk_div) * PERI_HCLK_HZ ==

• PERI_ACLK_HZ && (hclk_div < 0x4));
  

• pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
• assert((1 << pclk_div) * PERI_PCLK_HZ ==

• PERI_ACLK_HZ && pclk_div < 0x8);
  

• rk_clrsetreg(&cru->cru_clksel_con[10],

•      PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
  

•      PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
  

•      PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
  

•      pclk_div << PERI_PCLK_DIV_SHIFT |
  

•      hclk_div << PERI_HCLK_DIV_SHIFT |
  

•      aclk_div << PERI_ACLK_DIV_SHIFT);
  

• /* PLL enter normal-mode */
• rk_clrsetreg(&cru->cru_mode_con,

•      GPLL_MODE_MASK | APLL_MODE_MASK,
  

•      GPLL_MODE_NORM << GPLL_MODE_SHIFT |
  

•      APLL_MODE_NORM << APLL_MODE_SHIFT);
  

+}

+/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,

• 		   enum rk_clk_id clk_id)
  

+{

• uint32_t refdiv, fbdiv, postdiv1, postdiv2;
• uint32_t con;
• int pll_id = rk_pll_id(clk_id);
• struct rk322x_pll *pll = &cru->pll[pll_id];
• static u8 clk_shift[CLK_COUNT] = {

• 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
  

• GPLL_MODE_SHIFT, 0xff
  

• };
• static u32 clk_mask[CLK_COUNT] = {

• 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
  

• GPLL_MODE_MASK, 0xff
  

• };
• uint shift;
• uint mask;
• con = readl(&cru->cru_mode_con);
• shift = clk_shift[clk_id];
• mask = clk_mask[clk_id];
• switch ((con & mask) >> shift) {
• case GPLL_MODE_SLOW:

• return OSC_HZ;
  

• case GPLL_MODE_NORM:

• /* normal mode */
  

• con = readl(&pll->con0);
  

• postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
  

• fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
  

• con = readl(&pll->con1);
  

• postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
  

• refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
  

• return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  

• default:

• return 32768;
  

• }

+}

+static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,

• 		  int periph)
  

+{

• uint src_rate;
• uint div, mux;
• u32 con;
• switch (periph) {
• case HCLK_EMMC:
• case SCLK_EMMC:

• con = readl(&cru->cru_clksel_con[11]);
  

• mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  

• con = readl(&cru->cru_clksel_con[12]);
  

• div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  

• break;
  

• case HCLK_SDMMC:
• case SCLK_SDMMC:

• con = readl(&cru->cru_clksel_con[11]);
  

• mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  

• div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  

• break;
  

• default:

• return -EINVAL;
  

• }
• src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
• return DIV_TO_RATE(src_rate, div);

+}

+static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,

• 		  int periph, uint freq)
  

+{

• int src_clk_div;
• int mux;
• debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
• /* mmc clock auto divide 2 in internal */
• src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
• if (src_clk_div > 0x7f) {

• src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
  

• mux = EMMC_SEL_24M;
  

• } else {

• mux = EMMC_SEL_GPLL;
  

• }
• switch (periph) {
• case HCLK_EMMC:
• case SCLK_EMMC:

• rk_clrsetreg(&cru->cru_clksel_con[11],
  

• 	     EMMC_PLL_MASK,
  

• 	     mux << EMMC_PLL_SHIFT);
  

• rk_clrsetreg(&cru->cru_clksel_con[12],
  

• 	     EMMC_DIV_MASK,
  

• 	     (src_clk_div - 1) << EMMC_DIV_SHIFT);
  

• break;
  

• case HCLK_SDMMC:
• case SCLK_SDMMC:

• rk_clrsetreg(&cru->cru_clksel_con[11],
  

• 	     MMC0_PLL_MASK | MMC0_DIV_MASK,
  

• 	     mux << MMC0_PLL_SHIFT |
  

• 	     (src_clk_div - 1) << MMC0_DIV_SHIFT);
  

• break;
  

• default:

• return -EINVAL;
  

• }
• return rockchip_mmc_get_clk(cru, clk_general_rate, periph);

+}

+static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate) +{

• struct pll_div dpll_cfg;
• /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
• switch (set_rate) {
• case 400*MHz:

• dpll_cfg = (struct pll_div)
  

• {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
  

• break;
  

• case 600*MHz:

• dpll_cfg = (struct pll_div)
  

• {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
  

• break;
  

• case 800*MHz:

• dpll_cfg = (struct pll_div)
  

• {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
  

• break;
  

• }
• /* pll enter slow-mode */
• rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,

•      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
  

• rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
• /* PLL enter normal-mode */
• rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,

•      DPLL_MODE_NORM << DPLL_MODE_SHIFT);
  

• return set_rate;

+} +static ulong rk322x_clk_get_rate(struct clk *clk) +{

• struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
• ulong rate, gclk_rate;
• gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
• switch (clk->id) {
• case 0 ... 63:

• rate = rkclk_pll_get_rate(priv->cru, clk->id);
  

• break;
  

• case HCLK_EMMC:
• case SCLK_EMMC:
• case HCLK_SDMMC:
• case SCLK_SDMMC:

• rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rate;

+}

+static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) +{

• struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
• ulong new_rate, gclk_rate;
• gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
• switch (clk->id) {
• case HCLK_EMMC:
• case SCLK_EMMC:
• case HCLK_SDMMC:
• case SCLK_SDMMC:

• new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
  

• 				clk->id, rate);
  

• break;
  

• case CLK_DDR:

• new_rate = rk322x_ddr_set_clk(priv->cru, rate);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return new_rate;

+}

+static struct clk_ops rk322x_clk_ops = {

• .get_rate = rk322x_clk_get_rate,
• .set_rate = rk322x_clk_set_rate,

+};

+static int rk322x_clk_ofdata_to_platdata(struct udevice *dev) +{

• struct rk322x_clk_priv *priv = dev_get_priv(dev);
• priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
• return 0;

+}

+static int rk322x_clk_probe(struct udevice *dev) +{

• struct rk322x_clk_priv *priv = dev_get_priv(dev);
• rkclk_init(priv->cru);
• return 0;

+}

+static int rk322x_clk_bind(struct udevice *dev) +{

• int ret;
• /* The reset driver does not have a device node, so bind it here */
• ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
• if (ret)

• debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
  

• return 0;

+}

+static const struct udevice_id rk322x_clk_ids[] = {

• { .compatible = "rockchip,rk3228-cru" },
• { }

+};

+U_BOOT_DRIVER(rockchip_rk322x_cru) = {

• .name = "clk_rk322x",
• .id = UCLASS_CLK,
• .of_match = rk322x_clk_ids,
• .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
• .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
• .ops = &rk322x_clk_ops,
• .bind = rk322x_clk_bind,
• .probe = rk322x_clk_probe,

+};

Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com