Map all resource for R5 to operate properly. The patch is done based on the commit 23f7b1a77602 ("armv7R: K3: am654: Enable MPU regions") which also map the whole 4GB at first and then change mapping for DDR.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/mach-zynqmp-r5/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c index b3402d718950..87c1d75f9f3c 100644 --- a/arch/arm/mach-zynqmp-r5/cpu.c +++ b/arch/arm/mach-zynqmp-r5/cpu.c @@ -11,11 +11,9 @@ DECLARE_GLOBAL_DATA_PTR;
struct mpu_region_config region_config[] = { - { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_1GB }, - { 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO, - O_I_WB_RD_WR_ALLOC, REGION_512MB }, - { 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO, + { 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, + SHARED_WRITE_BUFFERED, REGION_4GB }, + { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_1GB }, };
@@ -23,8 +21,7 @@ int arch_cpu_init(void) { gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
- setup_mpu_regions(region_config, sizeof(region_config) / - sizeof(struct mpu_region_config)); + setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
return 0; }