5 Nov
2015
5 Nov
'15
9:03 a.m.
On Wed, 2015-11-04 at 10:03 -0800, York Sun wrote:
This patch set revises the DDR driver to support higher speed for DDR4 under heavy load (two dual-rank DIMMs) for four-chipselect interleaving. Single quad-rank DIMM is not supported yet.
Hi York
Seeing these patches reminds me about something I have been mening to ask, Is it possible init the ddr controller/ddr ram (using ECC also) but still retain (parts of) memory contents?
I am looking at keeping data at the end of memory when performing a warm start, but still init the controll/ddr ram (without D_INIT set). This way one could pick up any changes to DDR timing if needed. Before reboot, ddr ram is set to Self Refresh(SR).
Jocke