On 02/14/2017 09:23 AM, Dalon Westergreen wrote:
When CSEL=0x0 the socfpga bootrom does not touch the clock configuration for the device. This can lead to a boot failure on warm resets. To address this, the bootrom is configured to run a bit of code in the last 4KB of onchip ram on a warm reset. This code puts the PLLs in bypass, disables the bootrom configuration to run the code snippet, and issues a warm reset to run the bootrom.
Signed-off-by: Dalon Westergreen dwesterg@gmail.com
arch/arm/mach-socfpga/Makefile | 2 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 22 ++++++- arch/arm/mach-socfpga/include/mach/reset_manager.h | 4 ++ .../arm/mach-socfpga/include/mach/system_manager.h | 7 ++- arch/arm/mach-socfpga/misc.c | 29 +++++++++ arch/arm/mach-socfpga/reset_clock_manager.S | 71 ++++++++++++++++++++++ 6 files changed, 132 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 809cd47..6876ccf 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,7 +8,7 @@
Please fix up these checkpatch errors: total: 17 errors, 4 warnings, 2 checks, 199 lines checked
Dinh