On Jun 30, 2005, at 10:13 AM, Charles J Gillan wrote:
Recently I have been studying the boot sequence for the 8540 based boards in U-Boot. I have a question on the location of the initial C stack.
As I understand it,
cpu/mpc85xx/start.Suses L1 data cache as the location for the C stack prior to the relocation into RAM.
CFG_INIT_RAM_ADDR is defined within the relevant "config" file for each 6540 based board.
I see in the 8540 User Manual that there is a register which can be used to position L2 cache in physical address space but there does not appear to be a similar register for L1 cache.
However, I see that in the init.S files, for each board, entries are placed into TLB0 for memory at address CFG_INIT_RAM_ADDR. This is declared as cacheable and non-garded.
Am I correct in thinking that this is all that is required to position the C run-time stack in L1 D-cache ?
That should be it. We decided to use the L1 cache and lock lines into it for the initial C stack since we know that the L1 cache would always be there on an e500 core and were not sure if the L2 would be available.
- kumar