Re: [U-Boot] [PATCH v2 40/56] rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)

On 26 July 2017 at 04:40, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:

As part of the DRAM initialisation process (running as part of the TPL stage) on the RK3368, we need to set up the DRAM PLL.

This implements support for configuring the PLL to for 1200, 1332 or 1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).

Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com

Changes in v2: None

drivers/clk/rockchip/clk_rk3368.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)

Reviewed-by: Simon Glass sjg@chromium.org