From: Ye Li ye.li@nxp.com
After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used.
Reviewed-by: Peng Fan peng.fan@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/ddr/imx/imx8ulp/ddr_init.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c index 9730dd6450..a5a9fd8d7c 100644 --- a/drivers/ddr/imx/imx8ulp/ddr_init.c +++ b/drivers/ddr/imx/imx8ulp/ddr_init.c @@ -129,8 +129,8 @@ int ddr_calibration(unsigned int fsp_table[3]) * Polling SIM LPDDR_CTRL2 Bit phy_freq_chg_req until be 1'b1 */ reg_val = readl(AVD_SIM_LPDDR_CTRL2); - phy_freq_req = (reg_val >> 7) & 0x1; - + /* DFS interrupt is set */ + phy_freq_req = ((reg_val >> 7) & 0x1) && ((reg_val >> 15) & 0x1); if (phy_freq_req) { phy_freq_type = reg_val & 0x1F; if (phy_freq_type == 0x00) { @@ -159,7 +159,11 @@ int ddr_calibration(unsigned int fsp_table[3]) if (freq_chg_pt == 2) freq_chg_cnt--; } - reg_val = readl(AVD_SIM_LPDDR_CTRL2); + + /* Hardware clear the ack on falling edge of LPDDR_CTRL2:phy_freq_chg_reg */ + /* Ensure the ack is clear before starting to poll request again */ + while ((readl(AVD_SIM_LPDDR_CTRL2) & BIT(6))) + ; } } while (1);