The commit b583348ca8c8 ("image: fit: Align hash output buffers") places the hash output buffer at the .bss section. However, AST2600 by default executes SPL in the NOR flash XIP way. This results in the hash output cannot be written to the buffer as it is located at the R/X only region.
We need to move the .bss section out of the SPL body to the DRAM space, where hash output can be written to. This patch includes: - Define the .bss section base and size - A new SPL linker script is added with a separate .bss region specified - Enable CONFIG_SPL_SEPARATE_BSS kconfig option
Signed-off-by: Chia-Wei Wang chiawei_wang@aspeedtech.com --- arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 94 +++++++++++++++++++++ configs/evb-ast2600_defconfig | 3 + include/configs/evb_ast2600.h | 3 + 3 files changed, 100 insertions(+) create mode 100644 arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds new file mode 100644 index 0000000000..22b4e16d35 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * (C) Copyright 2022 + * Chia-Wei Wang chiawei_wang@aspeedtech.com + */ + +MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE, + LENGTH = CONFIG_SPL_SIZE_LIMIT } +MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + *(.vectors) + CPUDIR/start.o (.text*) + *(.text*) + *(.glue*) + } > .nor + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } > .nor + + . = ALIGN(4); + .data : { + *(.data*) + } > .nor + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .nor + + . = ALIGN(4); + .binman_sym_table : { + __binman_sym_start = .; + KEEP(*(SORT(.binman_sym*))); + __binman_sym_end = .; + } > .nor + + . = ALIGN(4); + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } > .nor + + .end : + { + *(.__end) + } > .nor + + _image_binary_end = .; + + .bss : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .bss + + __bss_size = __bss_end - __bss_start; +} + +#if defined(IMAGE_MAX_SIZE) +ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \ + "SPL image too big"); +#endif + +#if defined(CONFIG_SPL_BSS_MAX_SIZE) +ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \ + "SPL image BSS too big"); +#endif + +#if defined(CONFIG_SPL_MAX_FOOTPRINT) +ASSERT(__bss_end - _start <= (CONFIG_SPL_MAX_FOOTPRINT), \ + "SPL image plus BSS too big"); +#endif diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index f84b723bbb..d19e1d79ec 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_DCACHE_OFF=y CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds" CONFIG_ARCH_ASPEED=y CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_SYS_MALLOC_LEN=0x2000000 @@ -35,6 +36,8 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000 +CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_TPL_SEPARATE_BSS is not set CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_RAM_SUPPORT=y diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index 3c2155da46..54abb29df9 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -10,6 +10,9 @@
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x83000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x01000000 + /* Misc */ #define STR_HELPER(s) #s #define STR(s) STR_HELPER(s)