cs1_row can handle the pmu via sys_reg2 and sys_reg3 while configuring the dram instead of just sys_reg2.
So, update cs1_row macro to make use of both sys_reg2, sys_reg3.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: YouMin Chen cym@rock-chips.com --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 10 ++++++++-- drivers/ram/rockchip/sdram_rk3399.c | 4 +++- 2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 3d1d5badb4..dc7275656e 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -53,8 +53,6 @@ #define SYS_REG_CS0_ROW_MASK 3 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) #define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \ - SYS_REG_CS1_ROW_SHIFT(ch)) #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) #define SYS_REG_BW_MASK 3 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch)) @@ -68,6 +66,14 @@ (5 + 2 * (ch)); \ } while (0)
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ + (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ + (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (4 + 2 * (ch)); \ + } while (0) + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg);
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 2408246d0d..772fde9732 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1027,10 +1027,12 @@ static void dram_all_config(struct dram_info *dram, sys_reg2 |= SYS_REG_ENC_RANK(info->rank, channel); sys_reg2 |= SYS_REG_ENC_COL(info->col, channel); sys_reg2 |= SYS_REG_ENC_BK(info->bk, channel); - sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel); sys_reg2 |= SYS_REG_ENC_BW(info->bw, channel); sys_reg2 |= SYS_REG_ENC_DBW(info->dbw, channel); SYS_REG_ENC_CS0_ROW(info->cs0_row, sys_reg2, sys_reg3, channel); + if (info->cs1_row) + SYS_REG_ENC_CS1_ROW(info->cs1_row, sys_reg2, + sys_reg3, channel);
ddr_msch_regs = dram->chan[channel].msch; noc_timing = &sdram_params->ch[channel].noc_timings;