5 Jan
2016
5 Jan
'16
10:07 p.m.
Hi Fabio,
On Tue, Jan 5, 2016 at 1:02 PM, Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam fabio.estevam@nxp.com
As per the AR8031 datasheet:
"For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied."
So do as suggested and also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros 8031 PHY driver can be loaded automatically.
This results in a simpler code.
Signed-off-by: Fabio Estevam fabio.estevam@nxp.com
Acked-by: Joe Hershberger joe.hershberger@ni.com