On 8/3/21 2:20 PM, Ashok Reddy Soma wrote:
Move tapdelay function calls to zynq_sdhci.c and make them static inline. zynqmp_tap_delay.h has function prototypes for the functions defined in tap_delays.c, which will not be needed anymore.
Remove tap_delays.c and zynqmp_tap_delay.h files.
Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com
Reviewed-by: Jaehoon Chung jh80.chung@samsung.com
Best Regards, Jaehoon Chung
(no changes since v3)
Changes in v3:
- Make the changes on top of patch 4/7 to move the code to zynq_sdhci.c
board/xilinx/zynqmp/Makefile | 2 - board/xilinx/zynqmp/tap_delays.c | 115 ------------------------------- drivers/mmc/zynq_sdhci.c | 108 ++++++++++++++++++++++++++++- include/zynqmp_tap_delay.h | 34 --------- 4 files changed, 107 insertions(+), 152 deletions(-) delete mode 100644 board/xilinx/zynqmp/tap_delays.c delete mode 100644 include/zynqmp_tap_delay.h
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 7d8277ca40..a914028753 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -44,8 +44,6 @@ $(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_C endif endif
-obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o
ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_ZYNQMP) += cmds.o endif diff --git a/board/xilinx/zynqmp/tap_delays.c b/board/xilinx/zynqmp/tap_delays.c deleted file mode 100644 index 514f86a29a..0000000000 --- a/board/xilinx/zynqmp/tap_delays.c +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*
- Xilinx ZynqMP SoC Tap Delay Programming
- Copyright (C) 2018 Xilinx, Inc.
- */
-#include <common.h> -#include <zynqmp_tap_delay.h> -#include <asm/arch/sys_proto.h> -#include <asm/cache.h> -#include <linux/delay.h> -#include <mmc.h> -#include <zynqmp_firmware.h>
-#define SD_DLL_CTRL 0xFF180358 -#define SD_ITAP_DLY 0xFF180314 -#define SD_OTAP_DLY 0xFF180318 -#define SD0_DLL_RST BIT(2) -#define SD1_DLL_RST BIT(18) -#define SD0_ITAPCHGWIN BIT(9) -#define SD1_ITAPCHGWIN BIT(25) -#define SD0_ITAPDLYENA BIT(8) -#define SD1_ITAPDLYENA BIT(24) -#define SD0_ITAPDLYSEL_MASK GENMASK(7, 0) -#define SD1_ITAPDLYSEL_MASK GENMASK(23, 16) -#define SD0_OTAPDLYSEL_MASK GENMASK(5, 0) -#define SD1_OTAPDLYSEL_MASK GENMASK(21, 16)
-int zynqmp_dll_reset(u8 node_id, u32 type) -{
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,type == PM_DLL_RESET_ASSERT ?SD0_DLL_RST : 0);return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,type == PM_DLL_RESET_ASSERT ?SD1_DLL_RST : 0);- } else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,IOCTL_SD_DLL_RESET, type, 0, NULL);- }
-}
-int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay) -{
- int ret;
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0) {ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,SD0_ITAPCHGWIN);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,SD0_ITAPDLYENA);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY,SD0_ITAPDLYSEL_MASK,itap_delay);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);if (ret)return ret;}ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,SD1_ITAPCHGWIN);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,SD1_ITAPDLYENA);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,(itap_delay << 16));if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);if (ret)return ret;- } else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,IOCTL_SET_SD_TAPDELAY,PM_TAPDELAY_INPUT, itap_delay, NULL);- }
- return 0;
-}
-int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay) -{
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)return zynqmp_mmio_write(SD_OTAP_DLY,SD0_OTAPDLYSEL_MASK,otap_delay);return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,(otap_delay << 16));- } else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,IOCTL_SET_SD_TAPDELAY,PM_TAPDELAY_OUTPUT, otap_delay, NULL);- }
-} diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 8397f24255..9a1693940a 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -15,9 +15,9 @@ #include <dm/device_compat.h> #include <linux/err.h> #include <linux/libfdt.h> +#include <asm/cache.h> #include <malloc.h> #include <sdhci.h> -#include <zynqmp_tap_delay.h> #include <zynqmp_firmware.h>
#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8 @@ -31,6 +31,20 @@ #define SDHCI_TUNING_LOOP_COUNT 40 #define MMC_BANK2 0x2
+#define SD_DLL_CTRL 0xFF180358 +#define SD_ITAP_DLY 0xFF180314 +#define SD_OTAP_DLY 0xFF180318 +#define SD0_DLL_RST BIT(2) +#define SD1_DLL_RST BIT(18) +#define SD0_ITAPCHGWIN BIT(9) +#define SD1_ITAPCHGWIN BIT(25) +#define SD0_ITAPDLYENA BIT(8) +#define SD1_ITAPDLYENA BIT(24) +#define SD0_ITAPDLYSEL_MASK GENMASK(7, 0) +#define SD1_ITAPDLYSEL_MASK GENMASK(23, 16) +#define SD0_OTAPDLYSEL_MASK GENMASK(5, 0) +#define SD1_OTAPDLYSEL_MASK GENMASK(21, 16)
struct arasan_sdhci_clk_data { int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; @@ -49,6 +63,12 @@ struct arasan_sdhci_priv { u8 no_1p8; };
+/* For Versal platforms zynqmp_mmio_write() won't be available */ +__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) +{
- return 0;
+}
#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) /* Default settings for ZynqMP Clock Phases */ static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, @@ -76,6 +96,92 @@ static const u8 mode2timing[] = { [MMC_HS_200] = MMC_TIMING_MMC_HS200, };
+static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay) +{
- int ret;
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0) {ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,SD0_ITAPCHGWIN);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,SD0_ITAPDLYENA);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,itap_delay);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);if (ret)return ret;}ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,SD1_ITAPCHGWIN);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,SD1_ITAPDLYENA);if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,(itap_delay << 16));if (ret)return ret;ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);if (ret)return ret;- } else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,IOCTL_SET_SD_TAPDELAY,PM_TAPDELAY_INPUT, itap_delay, NULL);- }
- return 0;
+}
+static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay) +{
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)return zynqmp_mmio_write(SD_OTAP_DLY,SD0_OTAPDLYSEL_MASK,otap_delay);return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,(otap_delay << 16));- } else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,IOCTL_SET_SD_TAPDELAY,PM_TAPDELAY_OUTPUT, otap_delay, NULL);- }
+}
+static inline int zynqmp_dll_reset(u8 node_id, u32 type) +{
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,type == PM_DLL_RESET_ASSERT ?SD0_DLL_RST : 0);return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,type == PM_DLL_RESET_ASSERT ?SD1_DLL_RST : 0);- } else {
return xilinx_pm_request(PM_IOCTL, (u32)node_id,IOCTL_SD_DLL_RESET, type, 0, NULL);- }
+}
static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 node_id) { struct mmc *mmc = (struct mmc *)host->mmc; diff --git a/include/zynqmp_tap_delay.h b/include/zynqmp_tap_delay.h deleted file mode 100644 index 7ef172f0fa..0000000000 --- a/include/zynqmp_tap_delay.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/*
- Xilinx ZynqMP SoC Tap Delay Programming
- Copyright (C) 2018 Xilinx, Inc.
- */
-#ifndef __ZYNQMP_TAP_DELAY_H__ -#define __ZYNQMP_TAP_DELAY_H__
-#include <zynqmp_firmware.h>
-#ifdef CONFIG_ARCH_ZYNQMP -int zynqmp_dll_reset(u8 node_id, u32 type); -int arasan_zynqmp_set_in_tapdelay(u8 device_id, u32 itap_delay); -int arasan_zynqmp_set_out_tapdelay(u8 device_id, u32 otap_delay); -#else -inline int zynqmp_dll_reset(u8 deviceid, u32 type) -{
- return 0;
-}
-inline int arasan_zynqmp_set_in_tapdelay(u8 device_id, u32 itap_delay) -{
- return 0;
-}
-inline int arasan_zynqmp_set_out_tapdelay(u8 device_id, u32 otap_delay) -{
- return 0;
-} -#endif
-#endif