I have a ported u-boot base on 8548CDS for my 8548 board. The U-Boot version is 2008.10. the u-boot boot up was successful. I am trying to use BDI2000 do some debuging.
the BDI2000 config file is as below. with this config file, I can flash program and bring up my board. However, when I try to set a hardware break point, the u-boot code halt before it reach the break point.
###########config file############## ;bdiGDB configuration file for TF8548 Prototype [INIT] ; Errata PCI-Ex 26 workaround WM32 0xFF70A000 0x0000005C ;Clear bit 1 & 0 in Link Control & Status Register WM32 0xFF70A004 0x00000000 ;(PCIconfiguration space register at offset 0x5C) WM32 0xFF7E0F08 0x00000008 ;Clear bit 30 in the engineering only register ;(CCSR space register at offset 0xe0f08) ; use the following two lines for STARTUP HALT WSPR 63 0xffff0000 ;IVPR to boot core WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ;================= setup for flash programming =============== ; Move CCSRBAR to 0xe0000000 ; WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's to Match U-boot WM32 0xe0000C08 0x000f0000 ;LAWBAR0 : @0xc0000000 WM32 0xe0000C10 0x8040001b ;LAWAR0 : Local Bus 1Gb WM32 0xe0005000 0xff801001 ;BR0 16 bit at 0xff800000 WM32 0xe0005004 0xff801e65 ;OR0 ; ;================= end flash programming ===================== ; WM32 0xe00050d4 0x00030002 ;LCRR, LB clk /4 ;------------------------------- ; enable the memory interface ;------------------------------- ;; DDR_SDRAM_CFG;
;; CS0_BNDS WM32 0xe0002000 0x0000001f ; DDR CS0 for 512 MB Module ;; CS0_CONFIG WM32 0xe0002080 0x80000202 ; 14 Rows, 10 Columns for 512 MB ;; TIMING_CFG_0 WM32 0xe0002104 0x00260802 ; Match U-Boot Conclusion No Change ;; ext_refrec 0x00010000 ;; TIMING_CFG_1 WM32 0xe0002108 0x5d575533 ; For 512 MB Module 533MHz ;; TIMING_CFG_2 WM32 0xe000210C 0x049868cb ; 512MB 533MHz ;; DDR_SDRAM_MODE WM32 0xe0002118 0x00000842 ; 533MHz for 512 MB ; DDR_SDRAM_MODE2 0x00000000 ; DDR_SDRAM_INTERVAL WM32 0xe0002124 0x08210100 ; 512 MB 533MHz ; DDR_SDRAM_CFG2 WM32 0xe0002114 0x24000010 ; ; DDR_SDRAM_CLK_CNTL WM32 0xe0002130 0x03000000 ; 0110 3/4 - Works Reasonably (512MB PAtriot DEfault) DELAY 400
; enable the memory interface ; DDR_SDRAM_CFG ; enable the memory interface WM32 0xe0002110 0xe3008000 ; Match U-Boot Conclusion No change (ECC) ;define 2byte transfer size for flash memory TSZ2 0xff800000 0xffffffff
[TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;give reset time to complete POWERUP 2000 ;start delay after power-up detected in ms
[HOST] IP 192.168.0.113 FILE /BDI2000/u-boot.bin FORMAT BIN LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP dump PROMPT TF8548->>
[FLASH] CHIPTYPE AM29BX16 ;AM29LV641D CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE /u-boot.bin FORMAT BIN 0xFFF80000 ERASE 0xFFF80000 ;erase sector 0 ERASE 0xFFF90000 ;erase sector 1 ERASE 0xFFFa0000 ;erase sector 2 ERASE 0xFFFb0000 ;erase sector 3 ERASE 0xFFFc0000 ;erase sector 4 ERASE 0xFFFd0000 ;erase sector 5 ERASE 0xFFFe0000 ;erase sector 6 ERASE 0xFFFf0000 ;erase sector 7
[REGS] FILE /BDI2000/reg8548.def #########end of config file#########
for the u-boot debuging, #ppc-linux-gdb (gdb)add-symbol-file u-boot 0xfff80000 (gdb)target remote bdi2000:2001 (gdb)mon break hard (gdb)b board_init_r (gdb)c Continuing
My problem is the break point can't be reached. After Ctrl+C I can see the code halt at the line 224 in cpu_init_early_f shown as below
void cpu_init_early_f(void) { set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 0, BOOKE_PAGESZ_4K, 0);
/* set up CCSR if we want it moved */ #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) { u32 temp;
set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 1, BOOKE_PAGESZ_4K, 0);
=> temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12);
temp = in_be32((volatile u32 *)CFG_CCSRBAR); } #endif
/* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t));
init_laws(); invalidate_tlb(0); init_tlbs(); }
220 extern inline unsigned in_be32(const volatile unsigned __iomem *add 221 {
222 unsigned ret; 223
224 __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
225 "twi 0,%0,0;\n" 226 "isync" : "=r" (ret) : "m" (*addr)); 227 return ret; 228 }
I guess this is because that CFG_CCSRBAR_DEFAULT is not accessable. but the u-boot code did the set_tlb() already. Do i need to set tlb in the BDI2000 [INIT] section? what is the relationship between the u-boot and BDI2000 init procedure?