Re: [PATCH v5 10/14] riscv: sifive: fu540: add SPL configuration

On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel pragnesh.patel@sifive.com wrote:

Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper images from 1st partition of MMC boot devices.

SPL related code is leverage from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com

board/sifive/fu540/Kconfig | 8 +++ board/sifive/fu540/Makefile | 4 ++ board/sifive/fu540/fu540-memory-map.h | 23 ++++++++ board/sifive/fu540/fu540.c | 24 +++++++++ board/sifive/fu540/spl.c | 78 +++++++++++++++++++++++++++ include/configs/sifive-fu540.h | 18 +++++++ 6 files changed, 155 insertions(+) create mode 100644 board/sifive/fu540/fu540-memory-map.h create mode 100644 board/sifive/fu540/spl.c

diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 900197bbb2..ebe3472f9a 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME default "sifive-fu540"

config SYS_TEXT_BASE

•   default 0x80200000 if SPL
    default 0x80000000 if !RISCV_SMODE
    default 0x80200000 if RISCV_SMODE
  
  

+config SPL_TEXT_BASE

•   default 0x08000000
  

+config SPL_OPENSBI_LOAD_ADDR

•   default 0x80000000
  

config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV

•   select SUPPORT_SPL
    imply CMD_DHCP
    imply CMD_EXT2
    imply CMD_EXT4
  

diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile index 6e1862c475..b05e2f5807 100644 --- a/board/sifive/fu540/Makefile +++ b/board/sifive/fu540/Makefile @@ -3,3 +3,7 @@ # Copyright (c) 2019 Western Digital Corporation or its affiliates.

obj-y += fu540.o

+ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/sifive/fu540/fu540-memory-map.h b/board/sifive/fu540/fu540-memory-map.h new file mode 100644 index 0000000000..cba464652b --- /dev/null +++ b/board/sifive/fu540/fu540-memory-map.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright (c) 2019 SiFive, Inc
• */

+#ifndef FU540_MEMORY_MAP +#define FU540_MEMORY_MAP

+#include <asm/arch/gpio.h>

+/****************************************************************************

• • Platform definitions
• *****************************************************************************/

+/* Memory map */ +#define GPIO_CTRL_ADDR _AC(0x10060000, UL)

+/* Helper functions */ +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))

+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)

+#endif /* FU540_MEMORY_MAP */ diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c index 6c642b3082..89a65eb3fb 100644 --- a/board/sifive/fu540/fu540.c +++ b/board/sifive/fu540/fu540.c @@ -11,6 +11,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <misc.h> +#include <spl.h>

/*

• This define is a value used for error/unknown serial.

@@ -114,3 +115,26 @@ int board_init(void)

    return 0;

}

+#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{

•   u8 i;
  

•   u32 boot_devices[] = {
  

+#ifdef CONFIG_SPL_MMC_SUPPORT

•           BOOT_DEVICE_MMC1,
  

+#endif

•   };
  

•   for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
  

•           spl_boot_list[i] = boot_devices[i];
  

+} +#endif

+#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{

•   /* boot using first FIT config */
  

•   return 0;
  

+} +#endif diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c new file mode 100644 index 0000000000..522bc24753 --- /dev/null +++ b/board/sifive/fu540/spl.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (c) 2019 SiFive, Inc
• • Authors:
• • Pragnesh Patel pragnesh.patel@sifive.com
• */

+#include <common.h> +#include <spl.h> +#include <misc.h> +#include <dm.h>

+#include "fu540-memory-map.h"

+#define DDRCTLPLL_F 55 +#define DDRCTLPLL_Q 2

+#define PHY_NRESET 0x1000

+long nsec_per_cyc = 300; /* 33.333MHz */ +void nsleep(long nsec) +{

•   long step = nsec_per_cyc * 2;
  

•   while (nsec > 0)
  

•           nsec -= step;
  

+}

+void init_clk_and_ddr(void) +{

•   int ret;
  

•   struct udevice *dev;
  

•   /* PRCI init */
  

•   ret = uclass_get_device(UCLASS_CLK, 0, &dev);
  

•   if (ret) {
  

•           debug("Clock init failed: %d\n", ret);
  

•           return;
  

•   }
  

•   ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  

•   if (ret) {
  

•           printf("DRAM init failed: %d\n", ret);
  

•           return;
  

•   }
  

This should be split into two parts:

SoC specific parts should go to arch/riscv/fu540/spl.c, and board specific parts remain here.

Otherwise it's hard to re-use the same SPL codes for another board built on top of fu540.

•   /*
  

•    * GEMGXL init VSC8541 PHY reset sequence;
  

•    * leave pull-down active for 2ms
  

•    */
  

•   nsleep(2000000);
  

•   /* Set GPIO 12 (PHY NRESET) to OE=1 and OVAL=1 */
  

•   GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET;
  

•   GPIO_REG(GPIO_OUTPUT_EN) |= PHY_NRESET;
  

•   nsleep(100);
  

•   /* Reset PHY again to enter unmanaged mode */
  

•   GPIO_REG(GPIO_OUTPUT_VAL) &= ~PHY_NRESET;
  

•   nsleep(100);
  

•   GPIO_REG(GPIO_OUTPUT_VAL) |= PHY_NRESET;
  

•   nsleep(15000000);
  

+}

+void board_init_f(ulong dummy) +{

•   int ret;
  

•   ret = spl_early_init();
  

•   if (ret)
  

•           panic("spl_early_init() failed: %d\n", ret);
  

•   arch_cpu_init_dm();
  

•   init_clk_and_ddr();
  

•   preloader_console_init();
  

+}

Regards, Bin