The rk3288 edp node has a phy node in Linux with a clock property while current U-Boot driver expects this clock on position index 1. Move U-Boot-specific DT clock properties to rk3288-u-boot.dtsi and partially sync the edp node.
Signed-off-by: Johan Jonker jbx6244@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org # chromebook-jerry --- arch/arm/dts/rk3288-u-boot.dtsi | 5 +++++ arch/arm/dts/rk3288.dtsi | 17 +++++++++++------ 2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index e411445e..ca229150 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -91,6 +91,11 @@ u-boot,dm-pre-reloc; };
+&edp { + clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; + clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; +}; + &gpio7 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index f06d1f5b..9f924466 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -1177,19 +1177,24 @@ };
edp: dp@ff970000 { - compatible = "rockchip,rk3288-edp"; + compatible = "rockchip,rk3288-dp"; reg = <0xff970000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; - clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + phys = <&edp_phy>; + phy-names = "dp"; + power-domains = <&power RK3288_PD_VIO>; resets = <&cru SRST_EDP>; - reset-names = "edp"; + reset-names = "dp"; rockchip,grf = <&grf>; - power-domains = <&power RK3288_PD_VIO>; status = "disabled";
ports { - edp_in: port { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; edp_in_vopb: endpoint@0 { -- 2.20.1