This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it.
Cc: Valentin Longchamp valentin.longchamp@hitachi-powergrids.com Signed-off-by: Tom Rini trini@konsulko.com --- board/keymile/Kconfig | 1 - board/keymile/kmp204x/Kconfig | 20 -- board/keymile/kmp204x/MAINTAINERS | 6 - board/keymile/kmp204x/Makefile | 10 - board/keymile/kmp204x/ddr.c | 70 ----- board/keymile/kmp204x/eth.c | 71 ----- board/keymile/kmp204x/kmp204x.c | 265 ---------------- board/keymile/kmp204x/kmp204x.h | 8 - board/keymile/kmp204x/law.c | 39 --- board/keymile/kmp204x/pbi.cfg | 74 ----- board/keymile/kmp204x/pci.c | 125 -------- board/keymile/kmp204x/rcw_kmp204x.cfg | 11 - board/keymile/kmp204x/tlb.c | 109 ------- configs/kmcoge4_defconfig | 72 ----- include/configs/kmp204x.h | 416 -------------------------- 15 files changed, 1297 deletions(-) delete mode 100644 board/keymile/kmp204x/Kconfig delete mode 100644 board/keymile/kmp204x/MAINTAINERS delete mode 100644 board/keymile/kmp204x/Makefile delete mode 100644 board/keymile/kmp204x/ddr.c delete mode 100644 board/keymile/kmp204x/eth.c delete mode 100644 board/keymile/kmp204x/kmp204x.c delete mode 100644 board/keymile/kmp204x/kmp204x.h delete mode 100644 board/keymile/kmp204x/law.c delete mode 100644 board/keymile/kmp204x/pbi.cfg delete mode 100644 board/keymile/kmp204x/pci.c delete mode 100644 board/keymile/kmp204x/rcw_kmp204x.cfg delete mode 100644 board/keymile/kmp204x/tlb.c delete mode 100644 configs/kmcoge4_defconfig delete mode 100644 include/configs/kmp204x.h
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 86a667067de9..b76ad485f565 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -125,7 +125,6 @@ config SYS_IVM_EEPROM_PAGE_LEN
source "board/keymile/km83xx/Kconfig" source "board/keymile/kmcent2/Kconfig" -source "board/keymile/kmp204x/Kconfig" source "board/keymile/km_arm/Kconfig" source "board/keymile/pg-wcom-ls102xa/Kconfig"
diff --git a/board/keymile/kmp204x/Kconfig b/board/keymile/kmp204x/Kconfig deleted file mode 100644 index f74d4295c7ad..000000000000 --- a/board/keymile/kmp204x/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -if TARGET_KMP204X - -config SYS_BOARD - default "kmp204x" - -config SYS_VENDOR - default "keymile" - -config SYS_CONFIG_NAME - default "kmp204x" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_P2041 - select FSL_DDR_INTERACTIVE - select PHYS_64BIT - imply CMD_CRAMFS - imply FS_CRAMFS - -endif diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS deleted file mode 100644 index 8b9afffdc721..000000000000 --- a/board/keymile/kmp204x/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KMP204X BOARD -M: Valentin Longchamp valentin.longchamp@hitachi-powergrids.com -S: Maintained -F: board/keymile/kmp204x/ -F: include/configs/kmp204x.h -F: configs/kmcoge4_defconfig diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile deleted file mode 100644 index 5523ee99aae8..000000000000 --- a/board/keymile/kmp204x/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2001-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. - -obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o ../common/common.o\ - ../common/ivm.o ../common/qrio.o diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c deleted file mode 100644 index 77a00c55c951..000000000000 --- a/board/keymile/kmp204x/ddr.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp valentin.longchamp@keymile.com - * - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <i2c.h> -#include <hwconfig.h> -#include <init.h> -#include <log.h> -#include <asm/global_data.h> -#include <asm/mmu.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - if (ctrl_num) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - - /* automatic calibration for nb of cycles between read and DQS pre */ - popts->cpo_override = 0xFF; - - /* 1/2 clk delay between wr command and data strobe */ - popts->write_data_delay = 4; - /* clk lauched 1/2 applied cylcle after address command */ - popts->clk_adjust = 4; - /* 1T timing: command/address held for only 1 cycle */ - popts->twot_en = 0; - - /* we have only one module, half str should be OK */ - popts->half_strength_driver_enable = 1; - - /* wrlvl values overridden as recommended by ddr init func */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x6; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm; -} - -int dram_init(void) -{ - phys_size_t dram_size = 0; - - puts("Initializing with SPD\n"); - - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c deleted file mode 100644 index 29c5b339ae8c..000000000000 --- a/board/keymile/kmp204x/eth.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp valentin.longchamp@keymile.com - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <phy.h> - -int board_eth_init(struct bd_info *bis) -{ - int ret = 0; -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - - printf("Initializing Fman\n"); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - /* DTESC1/2 don't have a PHY, they are temporarily disabled - * so that u-boot doesn't try to unsuccessfuly enable them */ - fm_disable_port(FM1_DTSEC1); - fm_disable_port(FM1_DTSEC2); - - /* - * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf - * This is the debug interface, the only one used in u-boot - */ - fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); - fm_info_set_mdio(FM1_DTSEC5, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - - ret = cpu_eth_init(bis); - - /* reenable DTSEC1/2 for later (kernel) */ - fm_enable_port(FM1_DTSEC1); - fm_enable_port(FM1_DTSEC2); -#endif - - return ret; -} - -#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL) - -#define mv88E1118_PAGE_REG 22 - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) { - /* driver config is good */ - if (phydev->drv->config) - phydev->drv->config(phydev); - - /* but we still need to fix the LEDs */ - phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003); - phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840); - phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000); - } - - return 0; -} -#endif diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c deleted file mode 100644 index 29dde7a8024c..000000000000 --- a/board/keymile/kmp204x/kmp204x.c +++ /dev/null @@ -1,265 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp valentin.longchamp@keymile.com - * - * Copyright 2011,2012 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <fdt_support.h> -#include <image.h> -#include <init.h> -#include <netdev.h> -#include <linux/compiler.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <fm_eth.h> - -#include "../common/common.h" -#include "../common/qrio.h" -#include "kmp204x.h" - -static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; - -int checkboard(void) -{ - printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME); - - return 0; -} - -#define ZL30158_RST 8 -#define BFTIC4_RST 0 -#define RSTRQSR1_WDT_RR 0x00200000 -#define RSTRQSR1_SW_RR 0x00100000 - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - bool cpuwd_flag = false; - - /* configure mode for uP reset request */ - qrio_uprstreq(UPREQ_CORE_RST); - - /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ - setbits_be32(&gur->ddrclkdr, 0x001f000f); - - /* set reset reason according CPU register */ - if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) == - RSTRQSR1_WDT_RR) - cpuwd_flag = true; - - qrio_cpuwd_flag(cpuwd_flag); - /* clear CPU bits by writing 1 */ - setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR); - - /* set the BFTIC's prstcfg to reset at power-up and unit reset only */ - qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); - /* and enable WD on it */ - qrio_wdmask(BFTIC4_RST, true); - - /* set the ZL30138's prstcfg to reset at power-up only */ - qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST); - /* and take it out of reset as soon as possible (needed for Hooper) */ - qrio_prst(ZL30158_RST, false, false); - - return 0; -} - -int board_early_init_r(void) -{ - int ret = 0; - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - set_liodns(); - setup_qbman_portals(); - - ret = trigger_fpga_config(); - if (ret) - printf("error triggering PCIe FPGA config\n"); - - /* enable the Unit LED (red) & Boot LED (on) */ - qrio_set_leds(); - - /* enable Application Buffer */ - qrio_enable_app_buffer(); - - return 0; -} - -unsigned long get_board_sys_clk(unsigned long dummy) -{ - return 66666666; -} - -#define ETH_FRONT_PHY_RST 15 -#define QSFP2_RST 11 -#define QSFP1_RST 10 -#define ZL30343_RST 9 - -int misc_init_f(void) -{ - /* configure QRIO pis for i2c deblocking */ - i2c_deblock_gpio_cfg(); - - /* configure the front phy's prstcfg and take it out of reset */ - qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - qrio_prst(ETH_FRONT_PHY_RST, false, false); - - /* set the ZL30343 prstcfg to reset at power-up only */ - qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST); - /* and enable the WD on it */ - qrio_wdmask(ZL30343_RST, true); - - /* set the QSFPs' prstcfg to reset at power-up and unit rst only */ - qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST); - qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST); - - /* and enable the WD on them */ - qrio_wdmask(QSFP1_RST, true); - qrio_wdmask(QSFP2_RST, true); - - return 0; -} - -#define NUM_SRDS_BANKS 2 - -int misc_init_r(void) -{ - serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100, - SRDS_PLLCR0_RFCK_SEL_125}; - unsigned int i; - - /* check SERDES reference clocks */ - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 actual = in_be32(®s->bank[i].pllcr0); - actual &= SRDS_PLLCR0_RFCK_SEL_MASK; - if (actual != expected[i]) { - printf("Warning: SERDES bank %u expects reference \ - clock %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected[i]), - serdes_clock_to_string(actual)); - } - } - - ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, - CONFIG_PIGGY_MAC_ADDRESS_OFFSET); - return 0; -} - -#if defined(CONFIG_HUSH_INIT_VAR) -int hush_init_var(void) -{ - ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); - return 0; -} -#endif - -#if defined(CONFIG_LAST_STAGE_INIT) - -int last_stage_init(void) -{ -#if defined(CONFIG_KMCOGE4) - /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */ - struct bfticu_iomap *bftic4 = - (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE; - u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK; - - if (dip_switch != 0) { - /* start bootloader */ - puts("DIP: Enabled\n"); - env_set("actual_bank", "0"); - } -#endif - set_km_env(); - - return 0; -} -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -void fdt_fixup_fman_mac_addresses(void *blob) -{ - int node, i, ret; - char *tmp, *end; - unsigned char mac_addr[6]; - - /* get the mac addr from env */ - tmp = env_get("ethaddr"); - if (!tmp) { - printf("ethaddr env variable not defined\n"); - return; - } - for (i = 0; i < 6; i++) { - mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - - /* find the correct fdt ethernet path and correct it */ - node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000"); - if (node < 0) { - printf("no /soc/fman/ethernet path offset\n"); - return; - } - ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6); - if (ret) { - printf("error setting local-mac-address property\n"); - return; - } -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); - fdt_fixup_fman_mac_addresses(blob); -#endif - - return 0; -} - -#if defined(CONFIG_POST) - -/* DIC26_SELFTEST GPIO used to start factory test sw */ -#define SELFTEST_PORT QRIO_GPIO_A -#define SELFTEST_PIN 31 - -int post_hotkeys_pressed(void) -{ - qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN); - return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN); -} -#endif diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h deleted file mode 100644 index 3b858a557117..000000000000 --- a/board/keymile/kmp204x/kmp204x.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp valentin.longchamp@keymile.com - */ - - -void pci_of_setup(void *blob, struct bd_info *bd); diff --git a/board/keymile/kmp204x/law.c b/board/keymile/kmp204x/law.c deleted file mode 100644 index 2d83dfea15f8..000000000000 --- a/board/keymile/kmp204x/law.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp valentin.longchamp@keymile.com - * - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), -#endif - SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS - SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#endif -#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS - SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg deleted file mode 100644 index 3fdfb47ab235..000000000000 --- a/board/keymile/kmp204x/pbi.cfg +++ /dev/null @@ -1,74 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2012 Freescale Semiconductor, Inc. -# Refer docs/README.pblimage for more details about how-to configure -# and create PBL boot image -# - -#PBI commands -#Configure ALTCBAR for DCSR -> DCSR@89000000 -091380c0 000009C4 -09000010 00000000 -091380c0 000009C4 -09000014 00000000 -091380c0 000009C4 -09000018 81d00000 -#Workaround for A-004849 -091380c0 000009C4 -890B0050 00000002 -091380c0 000009C4 -890B0054 00000002 -091380c0 000009C4 -890B0058 00000002 -091380c0 000009C4 -890B005C 00000002 -091380c0 000009C4 -890B0090 00000002 -091380c0 000009C4 -890B0094 00000002 -091380c0 000009C4 -890B0098 00000002 -091380c0 000009C4 -890B009C 00000002 -091380c0 000009C4 -890B0108 00000012 -091380c0 000009C4 -#Workaround for A-006559 needed for rev 2.0 of P2041 silicon -89021008 0000f000 -091380c0 000009C4 -89021028 0000f000 -091380c0 000009C4 -89021048 0000f000 -091380c0 000009C4 -89021068 0000f000 -091380c0 000009C4 -#Flush PBL data -09138000 00000000 -#Disable ALTCBAR -09000018 00000000 -091380c0 000009C4 -#Initialize CPC1 as 1MB SRAM -09010000 00200400 -09138000 00000000 -091380c0 00000100 -09010100 00000000 -09010104 fff0000b -09010f00 08000000 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff00000 -09000d08 81000013 -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 27170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c deleted file mode 100644 index cdb498da03b0..000000000000 --- a/board/keymile/kmp204x/pci.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp valentin.longchamp@keymile.com - * - * Copyright 2007-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> -#include <linux/errno.h> - -#include "../common/qrio.h" -#include "kmp204x.h" - -#define PROM_SEL_L 11 -/* control the PROM_SEL_L signal*/ -static void toggle_fpga_eeprom_bus(bool cpu_own) -{ - qrio_gpio_direction_output(QRIO_GPIO_A, PROM_SEL_L, !cpu_own); -} - -#define CONF_SEL_L 10 -#define FPGA_PROG_L 19 -#define FPGA_DONE 18 -#define FPGA_INIT_L 17 - -int trigger_fpga_config(void) -{ - int ret = 0, init_l; - /* approx 10ms */ - u32 timeout = 10000; - - /* make sure the FPGA_can access the EEPROM */ - toggle_fpga_eeprom_bus(false); - - /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */ - qrio_gpio_direction_output(QRIO_GPIO_A, CONF_SEL_L, 0); - - /* trigger the config start */ - qrio_gpio_direction_output(QRIO_GPIO_A, FPGA_PROG_L, 0); - - /* small delay for INIT_L line */ - udelay(10); - - /* wait for FPGA_INIT to be asserted */ - do { - init_l = qrio_get_gpio(QRIO_GPIO_A, FPGA_INIT_L); - if (timeout-- == 0) { - printf("FPGA_INIT timeout\n"); - ret = -EFAULT; - break; - } - udelay(10); - } while (init_l); - - /* deassert FPGA_PROG, config should start */ - qrio_set_gpio(QRIO_GPIO_A, FPGA_PROG_L, 1); - - return ret; -} - -/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */ -static int wait_for_fpga_config(void) -{ - int ret = 0, done; - /* approx 5 s */ - u32 timeout = 500000; - - printf("PCIe FPGA config:"); - do { - done = qrio_get_gpio(QRIO_GPIO_A, FPGA_DONE); - if (timeout-- == 0) { - printf(" FPGA_DONE timeout\n"); - ret = -EFAULT; - goto err_out; - } - udelay(10); - } while (!done); - - printf(" done\n"); - -err_out: - /* deactive CONF_SEL and give the CPU conf EEPROM access */ - qrio_set_gpio(QRIO_GPIO_A, CONF_SEL_L, 1); - toggle_fpga_eeprom_bus(true); - - return ret; -} - -#define PCIE_SW_RST 14 -#define PEXHC_RST 13 -#define HOOPER_RST 12 - -void pci_init_board(void) -{ - qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - - /* wait for the PCIe FPGA to be configured - * it has been triggered earlier in board_early_init_r */ - if (wait_for_fpga_config()) - printf("error finishing PCIe FPGA config\n"); - - qrio_prst(PCIE_SW_RST, false, false); - qrio_prst(PEXHC_RST, false, false); - qrio_prst(HOOPER_RST, false, false); - /* Hooper is not direcly PCIe capable */ - mdelay(50); - - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg deleted file mode 100644 index 236d5138bc7e..000000000000 --- a/board/keymile/kmp204x/rcw_kmp204x.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for kmp204x boards -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -14600000 00000000 28200000 00000000 -148E70CF CFC02000 58000000 41000000 -00000000 00000000 00000000 F0428816 -00000000 00000000 00000000 00000000 diff --git a/board/keymile/kmp204x/tlb.c b/board/keymile/kmp204x/tlb.c deleted file mode 100644 index a268bd8e959c..000000000000 --- a/board/keymile/kmp204x/tlb.c +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp valentin.longchamp@keymile.com - * - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - /* TLB 1 */ - /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - /* QRIO */ - SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_64K, 1), - /* *I*G* - PCI1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_512M, 1), - /* *I*G* - PCI3 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_512M, 1), - /* *I*G* - PCI1&3 I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_128K, 1), -#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS - /* LBAPP1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), -#endif -#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS - /* LBAPP2 */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -#endif - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_4M, 1), -#endif -#ifdef CONFIG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_32K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig deleted file mode 100644 index 462e5677964e..000000000000 --- a/configs/kmcoge4_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xfff40000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020 -CONFIG_ENV_OFFSET_REDUND=0x110000 -CONFIG_MPC85xx=y -CONFIG_TARGET_KMP204X=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4" -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -CONFIG_MISC_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_JFFS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=fsl_elbc_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fsl_elbc_nand:-(ubi0);" -# CONFIG_CMD_IRQ is not set -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_DOS_PARTITION=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_DM=y -CONFIG_BOOTCOUNT_LIMIT=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_BCH=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h deleted file mode 100644 index af3b03be4909..000000000000 --- a/include/configs/kmp204x.h +++ /dev/null @@ -1,416 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp valentin.longchamp@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if defined(CONFIG_KMCOGE4) -#define CONFIG_HOSTNAME "kmcoge4" - -#else -#error ("Board not supported") -#endif - -#define CONFIG_KMP204X - -/* an additionnal option is required for UBI as subpage access is - * supported in u-boot - */ -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" - -#define CONFIG_NAND_ECC_BCH - -/* common KM defines */ -#include "km/keymile-common.h" - -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_SYS_DPAA_RMAN /* RMan */ - -/* Environment in SPI Flash */ -#define CONFIG_ENV_TOTAL_SIZE 0x020000 - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ - CONFIG_RAMBOOT_TEXT_BASE) -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/****************************************************************************** - * (PRAM usage) - * ... ------------------------------------------------------- - * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM - * ... |<------------------- pram -------------------------->| - * ... ------------------------------------------------------- - * @END_OF_RAM: - * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose - * @CONFIG_KM_PHRAM: address for /var - * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) - * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM - */ - -/* size of rootfs in RAM */ -#define CONFIG_KM_ROOTFSSIZE 0x0 -/* pseudo-non volatile RAM [hex] */ -#define CONFIG_KM_PNVRAM 0x80000 -/* physical RAM MTD size [hex] */ -#define CONFIG_KM_PHRAM 0x100000 -/* reserved pram area at the end of memory [hex] - * u-boot reserves some memory for the MP boot page - */ -#define CONFIG_KM_RESERVED_PRAM 0x1000 -/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable - * is not valid yet, which is the case for when u-boot copies itself to RAM - */ -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) - -/* - * Local Bus Definitions - */ - -/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) - -/* Nand Flash */ -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ - | OR_FCM_BCTLD /* LBCTL not ass */ \ - | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ - | OR_FCM_RST /* 1 clk read setup */ \ - | OR_FCM_PGS /* Large page size */ \ - | OR_FCM_CST) /* 0.25 command setup */ - -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ - -/* QRIO FPGA */ -#define CONFIG_SYS_QRIO_BASE 0xfb000000 -#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull - -#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ - | BR_PS_8 /* Port Size 8 bits */ \ - | BR_DECC_OFF /* no error corr */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ - | OR_GPCM_BCTLD /* no LCTL assert */ \ - | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ - | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ - | OR_GPCM_TRLX /* relaxed tmgs */ \ - | OR_GPCM_EAD) /* extra bus clk cycles */ - -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600) - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* I2C */ -/* QRIO GPIOs used for deblocking */ -#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A -#define KM_I2C_DEBLOCK_SCL 20 -#define KM_I2C_DEBLOCK_SDA 21 - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ -#define CONFIG_SYS_NUM_I2C_BUSES 3 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ - } - -#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -/* Default address of microcode for the Linux Fman driver - * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) - * ucode is stored after env, so we got 0x120000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x120000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC5" - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Hardware Watchdog - */ -#define CONFIG_WATCHDOG /* enable CPU watchdog */ -#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ -#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ - -/* - * additionnal command line configuration. - */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#define __USB_PHY_TYPE utmi -#define CONFIG_USB_EHCI_FSL - -/* - * Environment Configuration - */ -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -/* architecture specific default bootargs */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" - -/* FIXME: FDT_ADDR is unspecified */ -#define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \ - "update=" \ - "sf probe 0;sf erase 0 +${filesize};" \ - "sf write ${load_addr_r} 0 ${filesize};\0" \ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "" - -#define CONFIG_HW_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ - "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "usb_dr_mode=host\0" - -#define CONFIG_KM_NEW_ENV \ - "newenv=sf probe 0;" \ - "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ - __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" - -/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - CONFIG_KM_NEW_ENV \ - CONFIG_HW_ENV_SETTINGS \ - "EEprom_ivm=pca9547:70:9\0" \ - "" - -/* App2 Local bus */ -#define CONFIG_SYS_LBAPP2_BASE 0xE0000000 -#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull - -#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \ - | BR_PS_8 /* Port Size 8 bits */ \ - | BR_DECC_OFF /* no error corr */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ - | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \ - | OR_GPCM_CSNT /* LCS 1/4 clk before */ \ - | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ - | OR_GPCM_TRLX /* relaxed tmgs */ \ - | OR_GPCM_EAD) /* extra bus clk cycles */ -/* Local bus app2 Base Address */ -#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM -/* Local bus app2 Options */ -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM - -#endif /* __CONFIG_H */