Hi Rick,
On Fri, Jul 26, 2019 at 12:32 PM Rick Chen rickchen36@gmail.com wrote:
Hi Sagar
From: Sagar Kadam [mailto:sagar.kadam@sifive.com] Sent: Friday, July 19, 2019 7:37 PM To: Rick Jian-Zhi Chen(陳建志) Subject: Re: [U-Boot] [PATCH] riscv : serial: use rx watermark to indicate rx data is present
Hello Rick,
I missed to CC you while submitting the patch[1] Can you please provide your view's on the patch.
Sorry for the late response. I am OK with your patch. I will pull it into riscv tree ASAP :)
B.R Rick
Thanks for acknowledgement :)
Regards, Sagar
[1] https://patchwork.ozlabs.org/patch/1129736/
Thanks & Regards, Sagar Kadam
Thank you for the review and testing the changes.
On Fri, Jul 19, 2019 at 5:04 PM Sagar Kadam sagar.kadam@sifive.com wrote:
Hello Rick,
Sorry accidently pressed the send button after this :)
On Mon, Jul 15, 2019 at 5:52 PM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Padmarao,
On Mon, Jul 15, 2019 at 5:31 PM Padmarao Begari padmarao.b@gmail.com wrote:
Reviewed-by: Padmarao Begari padmarao.begari@microchip.com Tested-by: Padmarao Begari padmarao.begari@microchip.com
Regards Padmarao
BR, Sagar Kadam
On Tue, Jul 9, 2019 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
In y-modem transfer mode, tstc/getc fail to check if there is any data available / received in RX FIFO, and so y-modem transfer never succeeds. Using receive watermark bit within ip register fixes the issue.
This patch is based on commit c7392b7bc4e1 ("Use the RX watermark interrupt pending bit for TSTC") available at[1]
[1] https://github.com/sifive/HiFive_U-Boot/tree/regression
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com
drivers/serial/serial_sifive.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c index fdfef69..c142ccd 100644 --- a/drivers/serial/serial_sifive.c +++ b/drivers/serial/serial_sifive.c @@ -22,6 +22,9 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_TXCTRL_TXEN 0x1 #define UART_RXCTRL_RXEN 0x1
+/* IP register */ +#define UART_IP_RXWM 0x2
struct uart_sifive { u32 txfifo; u32 rxfifo; @@ -34,7 +37,6 @@ struct uart_sifive {
struct sifive_uart_platdata { unsigned long clock;
int saved_input_char; struct uart_sifive *regs; };@@ -94,7 +96,7 @@ static int _sifive_serial_getc(struct uart_sifive *regs) return -EAGAIN; ch &= UART_RXFIFO_DATA;
return (!ch) ? -EAGAIN : ch;
return ch;}
static int sifive_serial_setbrg(struct udevice *dev, int baudrate) @@ -133,7 +135,6 @@ static int sifive_serial_probe(struct udevice *dev) if (gd->flags & GD_FLG_RELOC) return 0;
platdata->saved_input_char = 0; _sifive_serial_init(platdata->regs); return 0;@@ -145,12 +146,6 @@ static int sifive_serial_getc(struct udevice *dev) struct sifive_uart_platdata *platdata = dev_get_platdata(dev); struct uart_sifive *regs = platdata->regs;
if (platdata->saved_input_char > 0) {c = platdata->saved_input_char;platdata->saved_input_char = 0;return c;}while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ; return c;@@ -171,14 +166,10 @@ static int sifive_serial_pending(struct udevice *dev, bool input) struct sifive_uart_platdata *platdata = dev_get_platdata(dev); struct uart_sifive *regs = platdata->regs;
if (input) {if (platdata->saved_input_char > 0)return 1;platdata->saved_input_char = _sifive_serial_getc(regs);return (platdata->saved_input_char > 0) ? 1 : 0;} else {
if (input)return (readl(®s->ip) & UART_IP_RXWM);else return !!(readl(®s->txfifo) & UART_TXFIFO_FULL);
}}
static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
2.7.4