Tom/Nishanth,
On Thu, Mar 12, 2015 at 10:57 AM, Fabio Estevam festevam@gmail.com wrote:
On Thu, Mar 12, 2015 at 10:41 AM, Tom Rini trini@konsulko.com wrote:
We should put this somewhere a bit more common that other A9 cores can also call into like OMAP4, SoCFPGA and maybe zynq later (based on a quick git grep pl310).
I thought about it as well, but I didn't find a suitable common place for putting it.
Suggestions? Thanks
What about this?
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 0f9d837..e3335f2 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -8,6 +8,7 @@ #include <linux/types.h> #include <common.h> #include <asm/armv7.h> +#include <asm/pl310.h> #include <asm/utils.h>
#define ARMV7_DCACHE_INVAL_ALL 1 @@ -274,8 +275,25 @@ void flush_dcache_range(unsigned long start, unsigned long stop) v7_outer_cache_flush_range(start, stop); }
+#ifdef CONFIG_SYS_L2_PL310 +static void pl310_set_override(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + + /* + * Set bit 22 in the auxiliary control register. If this bit + * is cleared, PL310 treats Normal Shared Non-cacheable + * accesses as Cacheable no-allocate. + */ + setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); +} +#endif + void arm_init_before_mmu(void) { +#ifdef CONFIG_SYS_L2_PL310 + pl310_set_override(); +#endif v7_outer_cache_enable(); invalidate_dcache_all(); v7_inval_tlb(); diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index ddc245b..de7650e 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -16,6 +16,8 @@ #define L2X0_STNDBY_MODE_EN (1 << 0) #define L2X0_CTRL_EN 1
+#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) + struct pl310_regs { u32 pl310_cache_id; u32 pl310_cache_type;