Hi Wenyou,
On 20 July 2017 at 02:13, Wenyou Yang wenyou.yang@microchip.com wrote:
From: Wenyou Yang wenyou.yang@atmel.com
The SAMA5D27-SiP (System in Package) integrates the SAMA5D2 with 1Gbit DDR2-SDRAM in a single package.
The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and Mac-address EEPROM.
Signed-off-by: Wenyou Yang wenyou.yang@microchip.com
arch/arm/dts/Makefile | 3 + arch/arm/dts/at91-sama5d27_som1_ek.dts | 155 ++++++++++++++++++ arch/arm/dts/sama5d2.dtsi | 20 +++ arch/arm/dts/sama5d27_som1.dtsi | 154 ++++++++++++++++++ arch/arm/mach-at91/Kconfig | 7 + board/atmel/sama5d27_som1_ek/Kconfig | 15 ++ board/atmel/sama5d27_som1_ek/MAINTAINERS | 6 + board/atmel/sama5d27_som1_ek/Makefile | 8 + board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 206 ++++++++++++++++++++++++ configs/sama5d27_som1_ek_mmc_defconfig | 82 ++++++++++ configs/sama5d27_som1_ek_spiflash_defconfig | 82 ++++++++++ include/configs/sama5d27_som1_ek.h | 100 ++++++++++++ 12 files changed, 838 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d27_som1_ek.dts create mode 100644 arch/arm/dts/sama5d27_som1.dtsi create mode 100644 board/atmel/sama5d27_som1_ek/Kconfig create mode 100644 board/atmel/sama5d27_som1_ek/MAINTAINERS create mode 100644 board/atmel/sama5d27_som1_ek/Makefile create mode 100644 board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c create mode 100644 configs/sama5d27_som1_ek_mmc_defconfig create mode 100644 configs/sama5d27_som1_ek_spiflash_defconfig create mode 100644 include/configs/sama5d27_som1_ek.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 033c1efd2b..a9fd0fae2b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -98,6 +98,12 @@ config TARGET_SAMA5D2_XPLAINED select SUPPORT_SPL select BOARD_EARLY_INIT_F
+config TARGET_SAMA5D27_SOM1_EK
bool "SAMA5D27 SOM1 EK board"select CPU_V7select SUPPORT_SPLselect BOARD_EARLY_INIT_F
Add help here to describe the board and peripherals.
config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" select CPU_V7 @@ -180,6 +186,7 @@ source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sama5d2_ptc/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" +source "board/atmel/sama5d27_som1_ek/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" diff --git a/board/atmel/sama5d27_som1_ek/Kconfig b/board/atmel/sama5d27_som1_ek/Kconfig new file mode 100644 index 0000000000..3276214d8c --- /dev/null +++ b/board/atmel/sama5d27_som1_ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D27_SOM1_EK
+config SYS_BOARD
default "sama5d27_som1_ek"+config SYS_VENDOR
default "atmel"+config SYS_SOC
default "at91"+config SYS_CONFIG_NAME
default "sama5d27_som1_ek"+endif diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS new file mode 100644 index 0000000000..609583c341 --- /dev/null +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -0,0 +1,6 @@ +SAMA5D27 SOM1 EK BOARD +M: Wenyou Yang wenyou.yang@microchip.com +S: Maintained +F: board/atmel/sama5d27_som1_ek/ +F: include/configs/sama5d27_som1_ek.h +F: configs/sama5d27_som1_ek_mmc_defconfig diff --git a/board/atmel/sama5d27_som1_ek/Makefile b/board/atmel/sama5d27_som1_ek/Makefile new file mode 100644 index 0000000000..4ab242c4ac --- /dev/null +++ b/board/atmel/sama5d27_som1_ek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Microchip Corporation +# Wenyou Yang wenyou.yang@microchip.com +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += sama5d27_som1_ek.o diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c new file mode 100644 index 0000000000..1d39b65a99 --- /dev/null +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -0,0 +1,206 @@ +/*
- Copyright (C) 2017 Microchip Corporation
Wenyou.Yang <wenyou.yang@microchip.com>
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h>
+DECLARE_GLOBAL_DATA_PTR;
+static void board_usb_hw_init(void) +{
atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);+}
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart1_hw_init(void) +{
atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */at91_periph_clk_enable(ATMEL_ID_UART1);+}
+void board_debug_uart_init(void) +{
board_uart1_hw_init();+} +#endif
+#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART
debug_uart_init();+#endif
return 0;+} +#endif
+int board_init(void) +{
/* address of boot parameters */gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;+#ifdef CONFIG_CMD_USB
board_usb_hw_init();+#endif
return 0;+}
+int dram_init(void) +{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,CONFIG_SYS_SDRAM_SIZE);return 0;+}
+#ifdef CONFIG_CMD_I2C +static int set_ethaddr_from_eeprom(void) +{
const int eth_addr_len = 6;unsigned char ethaddr[eth_addr_len];const char *ethaddr_name = "ethaddr";struct udevice *bus, *dev;if (getenv(ethaddr_name))return 0;if (uclass_get_device_by_seq(UCLASS_I2C, MAC24AA_I2C_BUS_NUM, &bus))return -1;if (dm_i2c_probe(bus, MAC24AA_ADDR, 0, &dev))return -1;if (dm_i2c_read(dev, MAC24AA_REG, ethaddr, eth_addr_len))
Is this an i2c eeprom? If so there is a DM driver for this.
return -1;if (!is_valid_ethaddr(ethaddr))return -1;return eth_setenv_enetaddr(ethaddr_name, ethaddr);+} +#endif
+#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_I2C
set_ethaddr_from_eeprom();+#endif
return 0;+} +#endif
+/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +}
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{
ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |ATMEL_MPDDRC_CR_NR_ROW_13 |ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |ATMEL_MPDDRC_CR_DIC_DS |ATMEL_MPDDRC_CR_ZQ_LONG |ATMEL_MPDDRC_CR_NB_8BANKS |ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |ATMEL_MPDDRC_CR_UNAL_SUPPORTED);ddrc->rtr = 0x511;ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |(3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |(9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |(3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |(4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |(4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |(2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |(23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |(200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |(3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |(8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |(4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |(4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |(8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
Looks like this should be in drivers/ram?
+}
+void mem_init(void) +{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;struct atmel_mpddrc_config ddrc_config;u32 reg;ddrc_conf(&ddrc_config);at91_periph_clk_enable(ATMEL_ID_MPDDRC);writel(AT91_PMC_DDR, &pmc->scer);reg = readl(&mpddrc->io_calibr);reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);writel(reg, &mpddrc->io_calibr);writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,&mpddrc->rd_data_path);ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);writel(0x3, &mpddrc->cal_mr4);writel(64, &mpddrc->tim_cal);+}
+void at91_pmc_init(void) +{
u32 tmp;/** while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz* so we need to slow down and configure MCKR accordingly.* This is why we have a special flavor of the switching function.*/tmp = AT91_PMC_MCKR_PLLADIV_2 |AT91_PMC_MCKR_MDIV_3 |AT91_PMC_MCKR_CSS_MAIN;at91_mck_init_down(tmp);tmp = AT91_PMC_PLLAR_29 |AT91_PMC_PLLXR_PLLCOUNT(0x3f) |AT91_PMC_PLLXR_MUL(40) |AT91_PMC_PLLXR_DIV(1);at91_plla_init(tmp);tmp = AT91_PMC_MCKR_H32MXDIV |AT91_PMC_MCKR_PLLADIV_2 |AT91_PMC_MCKR_MDIV_3 |AT91_PMC_MCKR_CSS_PLLA;at91_mck_init(tmp);
Should this be in the clock driver?
+} +#endif diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig new file mode 100644 index 0000000000..b6b84952f4 --- /dev/null
Regards, Simon