在2024年6月16日六月 下午5:00，Heinrich Schuchardt写道： [...]
The "LoongArch Reference Manual" is available at:
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_c...
What irritates me in 2.1.7.1. Cache Coherency Maintenance of Instruction Cache is the word *can*:
The Cache coherency maintenance between the instruction Cache and the data Cache within the processor core *can* be implemented as hardware maintenance.
Maybe you have to consult the Chinese version.
处理器核内部指令 Cache 与数据 Cache 之间的缓存一致性维护可以实现为硬件维护
The cache consistency maintenance between the instruction cache and data cache inside the processor core *can* be implemented as hardware maintenance.
Hi Heinrich,
Thanks for the investigation! Impressive effort on decrypting Chinese semantics :-)
I had consulted Loongson folks, and they told me that all current hardware implementation do have I/D cache coherency maintained by hardware, see implementation[1] in kernel.
For dcache I'll implement it with cac_op.
Thanks [1]: https://elixir.bootlin.com/linux/v6.9.5/source/arch/loongarch/mm/cache.c
Best regards
Heinrich